Senior FPGA Engineer, Space Networking & Security

Doist; San Jose (CA); Hybrid; USD 184,000 - 208,000; Full time

Job summary

Muon Space is seeking a Senior FPGA Engineer specialized in onboard networking, cryptography and security to design the network fabric and security architecture of our next-generation spacecraft. This hands-on role combines RTL coding with architectural influence.

Based in San Jose, CA, the position is hybrid, requiring on-site work three days per week. You will work with HPC and EE teams to deliver secure, high-speed FPGA-based networking for data movement from sensors to downlink.

Qualifications

• 5+ years of professional FPGA engineering experience in networking, cryptography, security, or high-speed I/O.
• Hands-on Ethernet, link aggregation, and signal integrity at high DAC rates.
• Experience implementing cryptographic algorithms in hardware/firmware (AES, AES-GCM, ECC, IPSec/VPN).

Responsibilities

• Define onboard networking architecture for switching, routing, filtering, firewalling, DPI, and VPN concepts.
• Define and implement end-to-end encryption, packet-based encryption at router level.
• Drive the onboard Ethernet switching device and evaluate options (COTS, semi-custom, FPGA-based).
• Design a NoC and robust FPGA-to-FPGA links with health monitoring.
• Own Ethernet PHY and MAC integration on FPGAs, link aggregation and SI trade-offs.
• Apply FEC schemes (e.g., Reed-Solomon) to onboard and inter-FPGA links.
• Integrate network fabric with customer payloads and validate links.
• Publish white papers and represent work internally/externally.
• Collaborate with Staff Onboard Compute Architect to harmonize networking with compute architecture.

Skills

FPGA engineering

Networking

Cryptography

Security

HDL/RTL (SystemVerilog Verilog VHDL)

Ethernet/Link aggregation

Security clearance eligible

Education

Bachelor's or Master's in CS/CE/EE

Tools

Verilog/SystemVerilog

VHDL

FPGA verification methodologies

Job description

Muon Space is seeking a Senior FPGA Engineer specialized in onboard networking, cryptography and security to design the network fabric and security architecture of our next-generation spacecraft. This hands-on role combines RTL coding with architectural influence.

Based in San Jose, CA, the position is hybrid, requiring on-site work three days per week. You will work with HPC and EE teams to deliver secure, high-speed FPGA-based networking for data movement from sensors to downlink.