Senior FPGA Engineer — Satellite & Space SoC

Owen Daniels; Chandler (AZ); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

3 weeks vacation

1 week personal

1 week sick leave

10 holidays (T4 Staff level)

full medical/dental/vision

Job summary

Owen Daniels is seeking a Senior FPGA Engineer to lead FPGA SoC development for satellite communications. You will design, integrate IP, and debug high-performance RTL for space-grade platforms, leveraging AMBA AXI/APB, PCIe, and Gigabit transceivers.

Ideal candidates have 5+ years in FPGA/SoC design, hands-on with Xilinx Vivado and Altera Quartus, and strong experience with simulation tools such as ModelSim or QuestaSim. US citizenship is required.

Qualifications

• BS in EE, CS, or equivalent; 5+ years' industry experience.
• FPGA design in VHDL/SystemVerilog; FPGA/ASIC SoC design experience.
• Strong hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim.
• SoC debug with AMBA AXI/APB interfaces; fmax-optimized IP.
• RTL simulation, Static Timing Analysis, and SDC.

Responsibilities

Skills

FPGA design (VHDL/SystemVerilog)

SoC design experience

AMBA AXI/APB interfaces

AXI-Stream IP

RTL simulation

Synthesis and STA (Timing)

Gigabit transceivers (PCIe/1000BASE-X)

Ethernet TCP/IP

Embedded C/C++

Git

Embedded Linux (bonus)

Education

BS in EE, CS, or equivalent

Tools

Xilinx Vivado

Altera Quartus

ModelSim/QuestaSim

Job description

Owen Daniels is seeking a Senior FPGA Engineer to lead FPGA SoC development for satellite communications. You will design, integrate IP, and debug high-performance RTL for space-grade platforms, leveraging AMBA AXI/APB, PCIe, and Gigabit transceivers.

Ideal candidates have 5+ years in FPGA/SoC design, hands-on with Xilinx Vivado and Altera Quartus, and strong experience with simulation tools such as ModelSim or QuestaSim. US citizenship is required.