Senior FPGA DSP Engineer for Space Communications

SWISSto12 SA; Northern, Foster City (KY, CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

SWISSto12 is seeking a senior DSP engineer to join the team and help develop, design, implement, and test advanced FPGA-based deployments for high-performance RF payloads.

The ideal candidate will have deep experience with signal processing algorithms, software-defined radios, and practical implementation on FPGA and SoC platforms. Location is United States (New York / New Jersey area); strong ownership and lab debugging skills are required.

Qualifications

• Master of Science in Electrical Engineering with focus on digital signal processing.
• Strong background in communication theory and wideband digitization.
• 7+ years of hands-on FPGA design and development experience for complex digital systems.
• Strong proficiency in synthesizable RTL design.
• Experience with Vivado, Vitis, equivalent toolchains.
• Extensive high speed serial interface design – JESD204B/C, PCIe Gen3/4, Ethernet, Aurora, equivalent SERDES protocols.
• Ability to partition problems and to define block level HW architectures, and extensive knowledge of VHDL.

Responsibilities

• Research and design of fast and efficient hardware realizable DSP algorithms to implement functions such as filters, equalizers, timing/carrier recover loops, multi-rate structures (Polyphase Filter Banks), FFT processing engines
• Development and utilize models that provide real life stimulus for testing the developed algorithms including phase and gaussian noise, non-linear RF effects, Doppler, multipath and other channel impairments
• Perform simulation, verification, hardware bring-up, lab debugging, timing analysis, and performance validation using FPGA vendor tools and test equipment.
• Collaborate with systems, RF, software, hardware, and test engineering teams to define requirements, interfaces, verification plans, and system integration approaches.
• Design and integrate high-speed serial interfaces including JESD204B/C, PCIe, Ethernet, Aurora, SERDES, DDR memory interfaces, and AXI-based data paths.
• Develop high-performance RTL using VHDL, Verilog, and/or SystemVerilog, with emphasis on timing closure, resource efficiency, scalability, and maintainability.
• Develop and maintain design documentation, interface control documents, verification reports, timing summaries, utilization reports, and reusable IP documentation.

Skills

Digital signal processing

Communication theory

FPGA design and development

RTL design

VHDL

Verilog

System-on-Chip FPGA platforms

Embedded processors

Linux-based software stacks

Lab debugging

Education

Master of Science in Electrical Engineering (DSP focus)

Tools

Vivado

Vitis

PCIe Gen3/4

JESD204B/C

Ethernet

AMD RFSoC

Zynq Ultrascale+

Job description

SWISSto12 is seeking a senior DSP engineer to join the team and help develop, design, implement, and test advanced FPGA-based deployments for high-performance RF payloads.

The ideal candidate will have deep experience with signal processing algorithms, software-defined radios, and practical implementation on FPGA and SoC platforms. Location is United States (New York / New Jersey area); strong ownership and lab debugging skills are required.