Senior FPGA Design Engineer - Space Avionics & Flight

Intuitive Machines, LLC

San Jose (CA)

On-site

USD 123,000 - 251,000

Full time

14 days+

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Benefits offered by this job

Health insurance
401(k)

Job summary

Lanteris Space Systems is seeking an FPGA Design Engineer to join the Bus Electronics Design team in San Jose, CA. You will lead FPGA design for avionics systems, collaborating across hardware and software teams to deliver high‑reliability space hardware from concept to flight.

The role requires deep RTL experience, IP integration, and a hands‑on approach in a fast‑paced environment with rigorous validation and qualification processes.

Qualifications

  • Must be a U.S. citizen or permanent resident.
  • Bachelor’s degree in electrical engineering, computer science, or a related field.
  • 8+ years FPGA design experience.
  • Proficiency in SystemVerilog and/or VHDL for RTL
  • Proficiency in configuring IP and integrating 3rd party IP.
  • Experience with FPGA synthesis, place-and-route, timing closures.

Responsibilities

  • Provide technical leadership on FPGA design choices and system trades.
  • Own FPGA development from concept through production and flight hardware.
  • Ensure high performance and reliable FPGA designs with fault tolerance and timing closure.
  • Collaborate with hardware and software teams for design bring‑up.
  • Document test plans and validate hardware through environmental testing.
  • Coordinate with cross‑functional teams to drive project success.

Skills

FPGA design
SystemVerilog/VHDL
RTL design
FPGA synthesis
fault tolerance
SerDes/SpaceWire

Education

Bachelor’s degree in electrical engineering or related

Tools

Xilinx Versal
Microchip RTAX/RTG4

Job description

Lanteris Space Systems is seeking an FPGA Design Engineer to join the Bus Electronics Design team in San Jose, CA. You will lead FPGA design for avionics systems, collaborating across hardware and software teams to deliver high‑reliability space hardware from concept to flight.

The role requires deep RTL experience, IP integration, and a hands‑on approach in a fast‑paced environment with rigorous validation and qualification processes.

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