Senior FPGA Design Engineer - Onsite with Secret Clearance

RTX; Austin (TX); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Relocation Assistance

9/8 Schedule – every other Friday off!

Job summary

RTX, the world's largest aerospace and defense company, seeks a Senior FPGA Design Engineer in the United States. You will design FPGA releases across VHDL/Verilog, leveraging Xilinx and Microsemi devices to deliver reliable, production-grade solutions and collaborate with systems engineers from requirements through integration.

You will mentor junior engineers, drive schedules, and contribute to design verification using UVM and constrained random methods, with a focus on RF/EO DSP, gigabit

Qualifications

• Degree in STEM with 5+ years of relevant experience.
• Experience with VHDL and/or Verilog coding.
• Experience with Xilinx or Microsemi devices and flow tools.

Responsibilities

• Design and deliver production quality FPGA releases from initial proof of concept to production.
• Architect FPGA-based systems including parts, interfaces, and CONOPS.
• Translate system requirements into FPGA requirements.
• Code in VHDL for reliability and maintainability.
• Verify designs with directed tests and constrained random tests; track coverage.
• Drive projects and manage schedules and budgets.
• Create documentation including requirements, test plans, and user guides.
• Lead small teams and mentor junior engineers.
• Support internal and external technical reviews.

Skills

VHDL coding

Verilog coding

SystemVerilog coding

Xilinx devices

Microsemi devices

Embedded ARM

Education

Bachelor's degree in STEM

Tools

UVM

Veloce

Simulation tools

Job description

RTX, the world's largest aerospace and defense company, seeks a Senior FPGA Design Engineer in the United States. You will design FPGA releases across VHDL/Verilog, leveraging Xilinx and Microsemi devices to deliver reliable, production-grade solutions and collaborate with systems engineers from requirements through integration.

You will mentor junior engineers, drive schedules, and contribute to design verification using UVM and constrained random methods, with a focus on RF/EO DSP, gigabit