Senior FPGA Design Engineer - DoD Secret Clearance Required

RTX; Albuquerque (NM); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Relocation Assistance

9/8 Schedule – every other Friday off

Job summary

RTX is seeking a Senior FPGA Design Engineer to develop FPGA designs across major vendors using VHDL, Verilog, and SystemVerilog. Responsibilities include translating requirements into FPGA architectures, implementing reliable code, and verifying designs with constrained random tests.

The role involves collaboration with circuit card designers and systems engineers, documentation, and mentoring junior engineers.

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
• Experience with VHDL and/or Verilog coding
• Experience with SystemVerilog coding
• Experience with Xilinx or Microsemi devices and flow tools

Responsibilities

• Design and deliver production quality FPGA releases from initial concept to production
• Architect FPGA-based systems to determine parts, interfaces, and CONOPS
• Translate system level requirements into FPGA requirements
• Design and code in VHDL for reliability and maintainability
• Verify designs utilizing directed and constrained random tests, while tracking functional and code coverage
• Help drive projects and execute program schedules on time and budget
• Create complete documentation including requirements, verification plan, and user’s guides
• Lead small teams and mentor junior engineers
• Support internal and external technical reviews

Skills

VHDL

Verilog

SystemVerilog

FPGA design

Embedded systems design

Education

Bachelor's degree in STEM

Tools

Xilinx flow tools

Microsemi flow tools

Job description

RTX is seeking a Senior FPGA Design Engineer to develop FPGA designs across major vendors using VHDL, Verilog, and SystemVerilog. Responsibilities include translating requirements into FPGA architectures, implementing reliable code, and verifying designs with constrained random tests.

The role involves collaboration with circuit card designers and systems engineers, documentation, and mentoring junior engineers.