Senior FPGA Design Engineer — Onsite (Fort Wayne, IN)

RTX; Fort Wayne (IN); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life Insurance

Short-term disability

Long-term disability

401(k) match

Flexible schedules

Employee assistance program

Employee Scholar Program

Parental leave

Paid time off

Holidays

Annual short-term incentive

Annual long-term incentive

Job summary

RTX in Fort Wayne, IN seeks a Senior FPGA Design Engineer to lead full‑lifecycle FPGA/ASIC design activities, from architecture through verification. You will define requirements, develop VHDL/Verilog code, perform timing closure, and mentor junior engineers in a multidisciplinary team environment.

The role emphasizes designing for reliability across multiple vendor devices, coordinating with program teams, and delivering well‑documented designs with strong CM practices.

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
• Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Hands on experience with integration and debug of FPGA/ASIC in a lab environment
• Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
• Experience with source code management, design reviews, and code release in a team development environment.

Responsibilities

• Provide full lifecycle support of production quality FPGA designs for major vendors and device families.
• Generate FPGA designs for gigabit serial interfaces, RF DSP, controls, data links, embedded processing and processor interfaces.
• Translate system level requirements into FPGA requirements.
• Architect FPGA-based systems to determine parts, interfaces and CONOPS.
• Lead FPGA designs and code in VHDL for reliability and maintainability.
• Verify designs with self-checking tests and track coverage.
• Define schedules for FPGA tasking and manage budgets and timelines.
• Create documentation including requirements, verification plan and user guides.
• Lead designs and/or small teams.
• Operate with minimal oversight from management.
• Support internal and external technical reviews.
• Mentor junior engineers.

Skills

FPGA/ASIC design

VHDL/Verilog

Xilinx/Altera/Microchip devices

Vivado/Quartus/Libero

Lab integration/debug

Timing closure

Source control

Education

Bachelor's degree in STEM

Advanced degree in EE or STEM

Tools

Vivado

Quartus Prime Pro

Libero

Job description

RTX in Fort Wayne, IN seeks a Senior FPGA Design Engineer to lead full‑lifecycle FPGA/ASIC design activities, from architecture through verification. You will define requirements, develop VHDL/Verilog code, perform timing closure, and mentor junior engineers in a multidisciplinary team environment.

The role emphasizes designing for reliability across multiple vendor devices, coordinating with program teams, and delivering well‑documented designs with strong CM practices.