Senior FPGA Design Engineer, High-Speed Networking

Arista Networks, Inc.; New Hampshire; On-site; USD 120,000 - 180,000; Full time

Job summary

Arista Networks is seeking an experienced FPGA Design Engineer to drive RTL/ SystemVerilog development for high-speed networking hardware used in data centers and campus networks. You will own the full design lifecycle from architectural requirements through verification, bring-up, and production deployment, collaborating with hardware, software, and manufacturing teams.

Qualifications emphasize 5+ years of Verilog/SystemVerilog RTL design, control path experience, and PCIe/AXI/I2C/SPI/MDIO

Qualifications

• 5+ years of hands-on Verilog/SystemVerilog RTL design.
• Proven background in control path design.
• Experience with on-chip bus interfaces such as PCIe, I2C, SPI, MDIO, AXI.
• Local to the New Hampshire area.

Responsibilities

• RTL Development & Verification: develop and verify Verilog and SystemVerilog RTL with custom testbenches.
• FPGA Flow Implementation: synthesize, place & route, timing closure, in-system debugging.
• System-Level Integration: collaborate with hardware/software teams for rapid bring-up.
• Design & Architecture Reviews: participate in RTL reviews and PCB reviews.
• Toolchain Automation: write Python/Tcl scripts to automate FPGA workflows.

Skills

Verilog/SystemVerilog RTL

Control Path design

On-Chip bus interfaces

Local to area

Job description

Arista Networks is seeking an experienced FPGA Design Engineer to drive RTL/ SystemVerilog development for high-speed networking hardware used in data centers and campus networks. You will own the full design lifecycle from architectural requirements through verification, bring-up, and production deployment, collaborating with hardware, software, and manufacturing teams.

Qualifications emphasize 5+ years of Verilog/SystemVerilog RTL design, control path experience, and PCIe/AXI/I2C/SPI/MDIO