Senior FPGA Design Engineer - High-Speed Networking

Arista

Nashua (NH)

On-site

USD 120,000 - 180,000

Full time

14 days+

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Job summary

Arista Networks in Nashua, NH is seeking a senior FPGA Design Engineer to drive RTL development and verification for high-speed networking platforms. You will own the full design lifecycle from requirements through production bring-up.

Work with cross-functional hardware, software, and manufacturing teams to deliver next-generation switch platforms. Requires 5+ years in Verilog/SystemVerilog RTL, control path design, and on-chip bus interfaces.

Qualifications

  • 5+ years of hands-on experience in Verilog/SystemVerilog RTL design.
  • Proven background in Control Path design.
  • Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
  • Local to the Nashua, NH area.

Responsibilities

  • RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code.
  • FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
  • System-Level Integration: Collaborate with hardware and software teams to drive bring-up and debugging of next-generation switch platforms.
  • Design & Architecture Reviews: Participate in RTL code reviews and board design reviews.
  • Toolchain Automation: Develop scripts to streamline data processing and FPGA design workflows.

Skills

Verilog/SystemVerilog RTL design
Control Path design
On-Chip Bus interfaces (I2C, SPI, MDIO
Local to the area

Job description

Arista Networks in Nashua, NH is seeking a senior FPGA Design Engineer to drive RTL development and verification for high-speed networking platforms. You will own the full design lifecycle from requirements through production bring-up.

Work with cross-functional hardware, software, and manufacturing teams to deliver next-generation switch platforms. Requires 5+ years in Verilog/SystemVerilog RTL, control path design, and on-chip bus interfaces.

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