FPGA Design Engineer – Data Center Networking + Equity

Arista; Roseville (CA); On-site; USD 110,000 - 170,000; Full time

Job summary

Arista Networks is seeking an experienced FPGA Design Engineer to drive the full lifecycle of high‑performance FPGA development for data center platforms. You will own RTL development, verification, and the end-to-end FPGA flow, collaborating with hardware and software teams to bring up next‑generation switch architectures.

The role emphasizes control path design, PCIe/AXI interfaces, and tight timing closure in a fast-paced data center environment.

Qualifications

• 5+ years of hands-on Verilog/SystemVerilog RTL design experience.
• Experience with control path design in high-speed networking hardware.
• Direct experience with on-chip bus interfaces (I2C, SPI, MDIO, PCIe, AXI).
• Local to the Bay area and able to work on site in the Bay Area.

Responsibilities

• RTL Development & Verification: develop, simulate, and verify Verilog/SystemVerilog RTL code including testbenches.
• FPGA Flow Implementation: full synthesis, place-and-route, timing closure, and hardware debugging.
• System-Level Integration: collaborate with hardware and software teams for rapid bring-up and debugging of network switch platforms.
• Design & Architecture Reviews: participate in RTL reviews and PCB/schematic reviews.
• Toolchain Automation: develop Python/Tcl scripts to automate FPGA design workflows.

Skills

Verilog/SystemVerilog RTL design

Control Path design

On-Chip Bus interfaces (I2C, SPI, MDIO

PCIe/AXI interfaces

Local to the Bay area

Python/Tcl scripting for EDA

Tools

Python scripting for EDA

Tcl scripting

Job description

Arista Networks is seeking an experienced FPGA Design Engineer to drive the full lifecycle of high‑performance FPGA development for data center platforms. You will own RTL development, verification, and the end-to-end FPGA flow, collaborating with hardware and software teams to bring up next‑generation switch architectures.

The role emphasizes control path design, PCIe/AXI interfaces, and tight timing closure in a fast-paced data center environment.