Senior FPGA Architect — Data Center Networking

Arista Networks, Inc.; California; On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical, Dental, Vision

Wellbeing programs

Bonuses and equity

Job summary

Arista Networks, Inc. is seeking a seasoned FPGA Design Engineer to join the Hardware Design Engineering team in California.

You will own the full design lifecycle for high-performance control path FPGAs powering Arista’s data center platforms, from requirements to verification and production support, collaborating with HW and SW teams. Role emphasizes RTL development in Verilog/SystemVerilog, FPGA flow, and system integration, with opportunities to work on PCIe, Ethernet, and AI-scale

Qualifications

• 5+ years of hands-on Verilog/SystemVerilog RTL design.
• Proven background in Control Path design.
• Direct experience with On-Chip Bus interfaces (e.g., PCIe, AXI, SPI, I2C, MDIO).
• Local to the Bay area.

Responsibilities

• RTL Development & Verification: Develop, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• System-Level Integration: Collaborate with hardware and software teams to drive bring-up and debugging of next-generation network switch platforms.
• Design & Architecture Reviews: Participate in peer RTL code reviews and PCB schematic reviews.
• Toolchain Automation: Develop Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.

Skills

Verilog/SystemVerilog RTL design

Control Path design

On-Chip bus interfaces (PCIe, AXI, etc

Python scripting

Tools

Python/Tcl/Shell scripting

Job description

Arista Networks, Inc. is seeking a seasoned FPGA Design Engineer to join the Hardware Design Engineering team in California.

You will own the full design lifecycle for high-performance control path FPGAs powering Arista’s data center platforms, from requirements to verification and production support, collaborating with HW and SW teams. Role emphasizes RTL development in Verilog/SystemVerilog, FPGA flow, and system integration, with opportunities to work on PCIe, Ethernet, and AI-scale