Senior FPGA Compiler & QoR Architect

Altera; San Jose (CA); Hybrid; USD 232,000 - 305,000; Full time

Job summary

Altera is seeking a Senior Principal Engineer to lead FPGA physical synthesis, timing optimization, and implementation methodologies. You will define architectural roadmaps, develop advanced optimization algorithms, and drive QoR improvements for large-scale FPGA/ASIC designs.

You will mentor engineers, collaborate with product management, and contribute to patentable innovations that shape Altera's tool suites and competitive position in the market.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field.
• 15+ years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies.
• Deep expertise in physical synthesis timing analysis logic synthesis placement and routing design optimization algorithms FPGA architecture and CAD flows.
• Demonstrated experience architecting large-scale software systems and optimization engines.
• Strong software development skills in C++, data structures, algorithms, and performance optimization.

Responsibilities

• Define and drive the architectural roadmap for FPGA compiler technologies.
• Design and develop advanced optimization algorithms focused on timing closure, area reduction, power optimization, routability, and runtime improvement.
• Lead development of next-generation timing driven optimization methodologies.
• Architect scalable solutions for large hierarchical designs and complex FPGA implementation flows.
• Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization domains.
• Partner with cross-functional engineering teams to integrate new technologies into production tool flows.
• Analyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities.
• Lead technical investigations of challenging timing and implementation problems across customer designs.
• Mentor engineers and provide technical leadership across architectural and algorithmic initiatives.
• Collaborate with product management and strategic customers to translate market needs into differentiated technology solutions.
• Contribute to patents, publications, and industry-leading innovations that strengthen Altera's competitive position.

Skills

C++

Data structures

Algorithms

Performance optimization

Software architecture

Education

BS/MS/PhD in EE/CS/CE or related field

Job description

Altera is seeking a Senior Principal Engineer to lead FPGA physical synthesis, timing optimization, and implementation methodologies. You will define architectural roadmaps, develop advanced optimization algorithms, and drive QoR improvements for large-scale FPGA/ASIC designs.

You will mentor engineers, collaborate with product management, and contribute to patentable innovations that shape Altera's tool suites and competitive position in the market.