Senior FPGA/ASIC Verification Lead — Secret Clearance

RTX (Raytheon); Fort Wayne (IN); Sur place; USD 120 000 - 180 000; Plein temps

Avantages offerts par ce poste

Medical, dental, and vision insurance

Three weeks of vacation

401(k) plan with employer matching

Résumé du poste

RTX seeks a Senior ASIC/FPGA Verification Engineer for its Fort Wayne, IN site. You will join the ART Microelectronics Technology team to verify high-performance RTL blocks across ASIC/FPGA designs using SystemVerilog and VHDL. Collaboration with design engineers and mentoring junior staff are key parts of the role.

The ideal candidate has a STEM degree with 5+ years of relevant experience or an advanced degree with at least 3 years, and holds an active U.S. government security clearance.

Qualifications

• Requires a STEM degree with 5+ years of experience or an advanced degree with 3+ years of experience.
• Active and transferable U.S. government security clearance required before start date.
• Experience developing and simulating RTL designs using VHDL and/or Verilog in FPGA/ASIC environments.
• Proven ability to design and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Knowledge of chip-level verification methodologies: constrained-random testing, functional coverage, assertion-based verification (SystemVerilog).
• Proficiency with Git or Subversion and revision control concepts.

Responsabilités

• Design verification environment architecture using SystemVerilog with OVM/UVM.
• Create test plans, test cases, and coverage tracking.
• Develop testbenches for RTL blocks using VHDL or SystemVerilog.
• Collaborate with design engineers to validate ASIC/FPGA solutions.
• Provide mentorship to junior engineers and potentially lead verification teams.

Connaissances

SystemVerilog

VHDL

Verilog

Testbenches

Git

Formation

STEM degree

Advanced degree

Outils

QuestaSim

Synplify

Quartus

Vivado

Description du poste

RTX seeks a Senior ASIC/FPGA Verification Engineer for its Fort Wayne, IN site. You will join the ART Microelectronics Technology team to verify high-performance RTL blocks across ASIC/FPGA designs using SystemVerilog and VHDL. Collaboration with design engineers and mentoring junior staff are key parts of the role.

The ideal candidate has a STEM degree with 5+ years of relevant experience or an advanced degree with at least 3 years, and holds an active U.S. government security clearance.