Senior FPGA/ASIC Verification Engineer

Mission Technologies, a division of HII

Roanoke (VA)

On-site

USD 120,000 - 170,000

Full time

14 days+

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Benefits offered by this job

Medical/Dental/Vision
Tuition reimbursement
401(k) plan

Job summary

Mission Technologies, a division of HII, seeks an FPGA/ASIC verification engineer to uncover corner-case bugs in gate-level netlists using Questa, VCS, and other industry tools. You will develop testbenches, write verification plans, and collaborate to deliver robust designs for mission-critical systems.

The role requires strong SystemVerilog/SystemC, C/C++, Python skills; familiarity with formal checkers and debug of complex digital blocks; U.S.

Qualifications

  • US Citizenship is required.
  • Willingness to obtain Top-Secret security clearance.
  • Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Experience with SystemVerilog, SystemC, C/C++, MATLAB.
  • Directed, constrained-random, and assertion-based verification techniques at multiple levels.
  • Experience with commercial simulators: Xcelium, Questa, VCS, Riviera-Pro, etc.
  • Scripting: Python, Bash, Tcl, make files.
  • Version control: Perforce, Git, SVN, etc.

Responsibilities

  • Develop models, transactors, stimuli, monitors, and test benches for simulating and uncovering hidden behaviors in gate-level digital netlists.
  • Produce clear documentation and test cases demonstrating identified bugs or deviations from the specification.
  • Effectively collaborate with teammates to produce cohesive results and create improved processes.

Skills

SystemVerilog
SystemC
C/C++
Python
MATLAB
Gate-level verification

Education

Electrical Engineering
Computer Engineering
Computer Science

Tools

Questa
VCS
Verdi
OneSpin 360EC
Xcelium
Incisive
Riviera-Pro

Job description

Mission Technologies, a division of HII, seeks an FPGA/ASIC verification engineer to uncover corner-case bugs in gate-level netlists using Questa, VCS, and other industry tools. You will develop testbenches, write verification plans, and collaborate to deliver robust designs for mission-critical systems.

The role requires strong SystemVerilog/SystemC, C/C++, Python skills; familiarity with formal checkers and debug of complex digital blocks; U.S.

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