Senior FPGA Architect for RFSoC DSP Systems

Fairwinds Technologies; United States; Hybrid; USD 150,000 - 210,000; Full time

Job summary

Fairwinds Technologies is seeking an FPGA Design Engineer to develop programmable logic for Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms using Verilog and VHDL. The role focuses on RTL design, verification, and integration with DSP and embedded software teams.

You will collaborate across RF, DSP, and embedded Linux domains to deliver high‑throughput signal processing and wideband RF solutions for DoD programs, while supporting prototype‑to‑production transitions and lab validation.

Qualifications

• Bachelor’s degree required in Electrical or Computer Engineering or related field.
• 10+ years of FPGA design and development experience.
• Proficiency in Verilog and/or VHDL.
• Experience with RTL simulation tools such as Questa and Vivado Simulator.
• Hands‑on Vivado synthesis/implementation/timing closure/debug.
• Experience with Zynq UltraScale+ RFSoC and Versal devices.
• Experience designing FPGA for PCB‑based embedded systems.
• Experience translating DSP specs into RTL implementations.
• Strong understanding of AXI, CDC, resets, and timing constraints.
• Experience with FPGA debugging tools such as ILA and JTAG.

Responsibilities

• Design, implement, and verify FPGA logic in Vivado for Zynq UltraScale+ RFSoC/Versal.
• Develop PL architectures for signal processing and high‑speed data movement.
• Implement DSP algorithms into RTL designs (filters, FFTs, channelizers).
• Define and implement PL–PS interfaces (AXI‑Lite/AXI‑Stream, DMA, interrupts).
• Integrate FPGA designs with embedded processors and heterogeneous compute architectures.
• Perform functional simulation, timing analysis, and resource optimization.
• Support FPGA bring‑up and debugging on PCB hardware with lab tools.
• Develop test benches, validation strategies, and design documentation.
• Support prototype‑to‑production transitions (ECOs, version control).
• Design interfaces with high‑speed data converters (ADRV9009, AD9081) and LVDS/JESD204B/C.

Skills

Verilog

VHDL

RTL simulation

AXI protocols

JTAG debugging

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Vivado

Questa sim

ILA

JESD204B/C

RFSoC (Zynq UltraScale+)

Versal

Job description

Fairwinds Technologies is seeking an FPGA Design Engineer to develop programmable logic for Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms using Verilog and VHDL. The role focuses on RTL design, verification, and integration with DSP and embedded software teams.

You will collaborate across RF, DSP, and embedded Linux domains to deliver high‑throughput signal processing and wideband RF solutions for DoD programs, while supporting prototype‑to‑production transitions and lab validation.