Senior Formal Verification Engineer - Cloud Hardware

Annapurna Labs; San Diego (CA); On-site; USD 213,000 - 288,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. seeks a Hardware Design Engineer to drive formal verification and IP/block ownership for next-generation cloud server infrastructure. You will work with partners and vendors to deliver high-performance, cost-efficient hardware in AWS data centers.

The role involves developing verification plans, modeling, and debugging RTL designs, plus collaboration with multiple engineering teams to optimize machine learning acceleration hardware such as AWS Inferentia.

Qualifications

• Bachelor's degree or above in computer science, electrical engineering, or related field.
• 7+ years of practical experience with formal verification as IP/Block owner, or equivalent academic experience in formal methods.
• 7+ years of experience with formal verification techniques including abstraction and end-to-end checking, or equivalent academic experience in formal methods.

Responsibilities

• Develop formal verification plans and verify IP architectures.
• Collaborate with block designers to understand micro-architectures.
• Develop checking algorithms, assertions, and FV models.
• Apply state-of-the-art formal methods and abstraction techniques.
• Participate in test plan and coverage reviews.
• Promote assertions to simulation and shape overall simulation strategy.
• Communicate with team across multiple disciplines.

Skills

Formal verification

RTL design

C/C++

C#

Node.js

Java

Python

Ruby

Abstraction techniques

Education

Bachelor's degree or higher in CS or EE

Tools

FV tools

Job description

Annapurna Labs (U.S.) Inc. seeks a Hardware Design Engineer to drive formal verification and IP/block ownership for next-generation cloud server infrastructure. You will work with partners and vendors to deliver high-performance, cost-efficient hardware in AWS data centers.

The role involves developing verification plans, modeling, and debugging RTL designs, plus collaboration with multiple engineering teams to optimize machine learning acceleration hardware such as AWS Inferentia.