Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Samsung Electronics GmbH; Mountain View (CA); On-site; USD 158,800 - 218,100; Full time

Job summary

Samsung Electronics GmbH in Mountain View, CA, is seeking a Senior Engineer to focus on SOC Architecture, specifically for Memory Subsystem and Interconnect. This role involves leading contributions to innovative designs for next-generation SOCs, emphasizing performance and power optimization.

The ideal candidate should possess a strong background in SOC or ASIC design, with specific experience in Fabric, System Cache, and DRAM controller architecture. Applicants are encouraged to apply if they meet the qualifications.

Qualifications

• 3+ years of experience in SOC or ASIC design and architecture.
• Prior direct experience in Fabric, System Cache, DRAM controller architecture or microarchitecture.
• Understanding of memory controller architecture, memory scheduling and prioritization.

Responsibilities

• Guide development of innovative Fabric, System cache and DRAM controller features.
• Evaluate architecture proposal benefits and communicate the results.
• Collaborate with silicon bring-up and product teams.

Skills

SOC or ASIC design and architecture

Fabric, System Cache, DRAM controller architecture

Memory controller architecture

ARM bus infrastructure (ACE/AXI/AHB)

JEDEC standards (LPDDR, DDR, HBM)

Performance modeling/simulation

Education

BSc, Masters, or PhD in Computer Science/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Job Location

Mountain View, CA

Job Type

Full-Time

Job #

402872

Job Department

Lab Summary: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high-performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

Position Summary

We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands‑on role leading individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

Position Responsibilities

• Guide development of innovative Fabric, System cache and DRAM controller architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
• Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
• Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
• Perform high‑level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex use cases
• Direct and orchestrate performance modeling and studies to support inclusion of these features in the next generation Fabric, System cache and DRAM controller microarchitecture based on performance, area or power improvement
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
• Collaborate with silicon bring‑up and product teams to verify and debug the proposal and its delivered performance
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentation

Required Skills

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 3+ years of experience in SOC or ASIC design and architecture
• Prior direct experience in Fabric, System Cache, DRAM controller architecture or microarchitecture is required
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

Special Attributes

• Experience with BookSim Simulator
• Experience with Platform Architect

Base Pay Range

$158,800 — $218,100 USD

Essential Job Functions

This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.

Equal Employment Opportunity

Samsung Research America is committed to employing a diverse workforce, and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Disclosure of Trade Secrets

Samsung has a strict policy on trade secrets. In applying to Samsung and progressing through the recruitment process, you must not disclose any trade secrets of a current or previous employer.

Pay Transparency

BPay Transparency