Sr Analog Design I& Layout Engineer (Microelectronic Commons)

Henpen Corporation; Santa Monica (CA); On-site; USD 108,000 - 180,000; Full time

Job summary

Henpen Corporation in Los Angeles, CA, seeks a versatile Senior Analog Design & Layout Engineer to bridge industry and academia. You will lead schematic capture, layout implementation, and tape-out across multiple process technologies, while mentoring advanced circuit design courses and supporting funded research projects.

You will drive post-layout verification, parasitic extraction, and layout closure, producing technical reports for partners and students.

Qualifications

• Education: Bachelor's, Master's, or PhD in Electrical Engineering or related field.
• Experience: 3+ years of professional experience in analog circuit design and/or physical layout.
• Tooling: Mastery of industry-standard CAD environments (e.g., Cadence Virtuoso, SPICE simulators, or Mentor Graphics).
• Verification: Deep understanding of layout verification methodologies and parasitic extraction.
• Communication: Exceptional interpersonal skills; ability to translate complex technical concepts for both customers and students.

Responsibilities

• Technical consulting & design support for high-performance analog or digital designs.
• Multi-process expertise across CMOS, BiCMOS, and III-V with strict foundry rule compliance.
• Academic & research integration: support tape-out curriculum and mentor students.
• Full lifecycle verification: post-layout simulation, parasitic extraction, and layout verification (DRC/LVS) for research projects.
• Collaborative documentation: author design reports and layout closure docs for industry partners and academia.

Skills

Analog circuit design

Physical layout

Schematic capture

Layout verification

Parasitic extraction

Communication

Education

Bachelor's, Master's, or PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE simulators

Mentor Graphics

Job description

The Opportunity

We are seeking a versatile Analog Design and Layout Engineer to join a premier microelectronics hub. This role is unique: you will function as a technical consultant for external customers, a mentor for advanced circuit design courses, and a key contributor to funded research. If you enjoy the intersection of hands‑on physical layout and academic innovation-moving from schematic capture to tape‑out across diverse process technologies-this is your ideal environment.

Key Responsibilities

• " Technical Consulting & Design Support: Partner with external customers to develop high-performance analog or digital circuit designs. You will provide expert guidance on schematic capture, simulation, and layout implementation.
• " Multi-Process Expertise: Navigate and implement designs across a variety of technologies, including CMOS, BiCMOS, and III-V, ensuring strict compliance with foundry design rules
• " Academic & Research Integration: Support specialized "tape‑out" curriculum by demonstrating advanced layout techniques and troubleshooting design‑flow bottlenecks for students.
• " Full Lifecycle Verification: Lead efforts in post-layout simulation, parasitic extraction, and layout verification (DRC/LVS) for high-impact research projects.
• " Collaborative Documentation: Author technical design reports and layout closure documentation for both industry partners and academic stakeholders.

Senior Analog Design & Layout Engineer (Microelectronic Commons)
Los Angeles,California, USA
157000-180000

The Opportunity

We are seeking a versatile Analog Design and Layout Engineer to join a premier microelectronics hub. This role is unique: you will function as a technical consultant for external customers, a mentor for advanced circuit design courses, and a key contributor to funded research. If you enjoy the intersection of hands‑on physical layout and academic innovation-moving from schematic capture to tape‑out across diverse process technologies-this is your ideal environment.

Key Responsibilities

• " Technical Consulting & Design Support: Partner with external customers to develop high-performance analog or digital circuit designs. You will provide expert guidance on schematic capture, simulation, and layout implementation.
• " Multi-Process Expertise: Navigate and implement designs across a variety of technologies, including CMOS, BiCMOS, and III-V, ensuring strict compliance with foundry design rules
• " Academic & Research Integration: Support specialized "tape‑out" curriculum by demonstrating advanced layout techniques and troubleshooting design‑flow bottlenecks for students.
• " Full Lifecycle Verification: Lead efforts in post-layout simulation, parasitic extraction, and layout verification (DRC/LVS) for high-impact research projects.
• " Collaborative Documentation: Author technical design reports and layout closure documentation for both industry partners and academic stakeholders.

Qualifications

Required Qualifications

• " Education: Bachelor's, Master's, or PhD in Electrical Engineering or a related technical field.
• " Experience: Minimum 3+ years of professional experience in analog circuit design and/or physical layout.
• " Tooling: Mastery of industry-standard CAD environments (e.g., Cadence Virtuoso, SPICE simulators, or Mentor Graphics).
• " Verification: Deep understanding of layout verification methodologies and parasitic extraction.
• " Communication: Exceptional interpersonal skills; ability to translate complex technical concepts for both customers and students.

Preferred Skills

• " Experience with device‑level, electromagnetic, or photonic component simulations.
• " Prior experience in a teaching, tutoring, or workshop‑led environment.

Why is This a Great Opportunity

This is part of the Microeletronics Commons effort to bring back integrated circuit design to the USA. Multple regions including academia and industry are working jointly to achieve this goal.