Senior Emulation Engineer

Prodapt; Sunnyvale (CA); On-site; USD 160,000 - 220,000; Full time

Job summary

Prodapt in Sunnyvale, CA seeks an experienced Senior Emulation/Verification Engineer to lead pre-silicon validation using hardware acceleration platforms. You will optimize environments on Cadence Palladium or Synopsys ZeBu and port SystemVerilog/UVM testbenches to emulation.

You will collaborate across RTL, Design Verification, Firmware, and Software teams to accelerate delivery, debug issues, and enable long-running regressions with scripting support.

Qualifications

• 10+ years in Design Verification, Hardware Emulation, or Simulation Acceleration for ASIC/SoC development.
• Strong expertise with Cadence Palladium and/or Synopsys ZeBu.
• Hands-on experience with SystemVerilog, UVM, and hardware emulation.
• Experience porting verification environments to acceleration platforms.
• RTL debugging, waveform analysis, and verification methodologies.
• Familiarity with VIP integration and custom transactor development.
• Scripting in Python, Perl, Tcl, or Shell.

Responsibilities

• Maintain and optimize simulation acceleration and emulation environments.
• Port SystemVerilog/UVM verification environments to hardware acceleration platforms.
• Partition verification environments between the host and emulator for performance and correctness.
• Optimize verification environments to reduce compile time and improve efficiency.
• Enable long-running regressions and software-driven validation on emulation platforms.
• Integrate third-party VIP and develop custom transactors.
• Debug RTL, testbench, and emulation issues using waveform analysis and tools.
• Collaborate with RTL, DV, Architecture, Firmware, and Software teams to accelerate delivery.

Skills

SystemVerilog

UVM

Hardware emulation

Design verification

RTL debugging

Scripting (Python/Perl/Tcl/Shell)

Regression automation

Education

Bachelor's or Master's degree in Electronics Engineering / Electrical Engineering / Computer Engineering / Computer Science

Tools

Cadence Palladium

Synopsys ZeBu

Emulation platforms

Job description

Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A "Great Place To Work® Certified™" company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

We are seeking an experienced Senior Emulation/Verification Engineer with expertise in simulation acceleration, hardware emulation, and SystemVerilog/UVM-based verification environments. The ideal candidate will have strong experience with Cadence Palladium and/or Synopsys ZeBu, enabling efficient pre-silicon verification and accelerating complex SoC validation.

Key Responsibilities

• Maintain and optimize simulation acceleration and emulation environments using Cadence Palladium and/or Synopsys ZeBu
• Port SystemVerilog/UVM verification environments to hardware acceleration and emulation platforms
• Partition verification environments between the host and emulator while ensuring functional correctness and optimal performance
• Optimize verification environments to reduce compile time and improve execution efficiency
• Enable long-running regressions and software-driven validation on emulation platforms
• Integrate third-party Verification IP (VIP) and develop custom transactors as required
• Debug RTL, testbench, and emulation-related issues using waveform analysis and emulator debug tools
• Collaborate with RTL, Design Verification, Architecture, Firmware, and Software teams to accelerate project delivery.

Required Skills

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related fields
• 10+ years of experience in Design Verification, Hardware Emulation, or Simulation Acceleration for ASIC/SoC development
• Strong expertise in Cadence Palladium and/or Synopsys ZeBu
• Hands-on experience with SystemVerilog, UVM, and hardware emulation
• Experience porting verification environments to acceleration platform
• Strong understanding of RTL debugging, waveform analysis, and verification methodologies
• Experience with VIP integration and custom transactor development
• Knowledge of simulation acceleration, emulation flows, and regression automation
• Familiarity with scripting using Python, Perl, Tcl, or Shell

Preferred Qualification

• Experience with complex SoC/IP verification
• Knowledge of firmware-assisted verification and software-driven validation
• Familiarity with CI/CD and regression automation
• Strong debugging, analytical, and problem-solving skills
• Excellent communication and cross-functional collaboration skills