Senior Electrical Link Architect – Co-Packaged Optics

Ayar Labs, Inc.; San Jose (CA); On-site; USD 224,000 - 262,000; Full time

Job summary

Ayar Labs, Inc. in San Jose, CA is seeking a Principal Engineer to own the end-to-end electrical path of the optical link from the analog front end to the DSP, including the development of models and verification for next-generation Co-Packaged Optics.

You will drive tapeout decisions, align block specs, and guide cross-functional teams. This role demands deep experience in high-speed SerDes, equalization, clock recovery, and statistical analysis, with strong Cadence tool fluency and Python for

Qualifications

• BS in Electrical Engineering, Physics, or a related field.
• 8+ years in high-speed wireline or optical link design, spanning both the analog front end and the equalization that closes the link.
• Hands-on design, or direct co-design, of analog front-end blocks (TIA, CTLE, VGA, sampler, TX driver, clocking) in a high-speed SerDes or optical transceiver, with a deep understanding of bandwidth, noise, linearity, jitter, offset, and swing.
• Strong command of equalization and clock recovery (CTLE, FFE, DFE, MLSE, ADC-based receivers, adaptation, CDR).
• Proficiency in Verilog-A and mixed-signal simulation; working fluency in Cadence Virtuoso / ADE / Spectre.
• Statistical circuit and link analysis (corners, Monte Carlo, BER and margin prediction) and strong Python for scientific computing.

Responsibilities

• Own the end-to-end electrical architecture of the optical link (driver through modulator, photodetector through TIA, analog front end, equalization, clock recovery) and the electrical link budget that goes with it.
• Decide how equalization and gain are partitioned between the analog front end and DSP, with power, area, and margin as explicit tradeoffs, and own that decision through tapeout.
• Translate link requirements into block-level electrical specs (bandwidth, noise, linearity, jitter, offset, swing) for the AMS design team, and sign off that the blocks as designed close the link at yield.
• Build the electrical models that matter: compact models of the analog front end and DSP chain at BER and link-margin fidelity, and Verilog-A models of the electrical/optical interface co-designed with AMS and photonics.
• Lead silicon correlation for the electrical path with validation and SerDes characterization; drive the model or the design to change when they disagree.
• Run statistical link analysis (corners, Monte Carlo, yield) in the team's in-house simulation stack; flag product specs that cannot be met and lay out the options.
• Own the exploration of next-generation electrical link architectures (data rate per lane, modulation format, DSP-light versus ADC-based receivers, new electrical/optical interfaces) and turn them into concrete tapeout recommendations and roadmap input.
• Represent the electrical link architecture in cross-functional reviews, customer engagements, and foundry/EDA partner discussions; mentor the team on analog front-end behavior.

Skills

High-speed SerDes design

Analog front-end design

Jitter and noise analysis

Python for scientific computing

Statistical circuit and link analysis

Verilog-A

Education

BS in Electrical Engineering, Physics, or related field

MS or PhD in Electrical Engineering, Physics, or related field

Tools

Cadence Virtuoso

Spectre

ADE

Python

Job description

Ayar Labs, Inc. in San Jose, CA is seeking a Principal Engineer to own the end-to-end electrical path of the optical link from the analog front end to the DSP, including the development of models and verification for next-generation Co-Packaged Optics.

You will drive tapeout decisions, align block specs, and guide cross-functional teams. This role demands deep experience in high-speed SerDes, equalization, clock recovery, and statistical analysis, with strong Cadence tool fluency and Python for