Senior Optical Link Design Engineer (Co-Packaged Optics)

InvestedintheMission; San Jose (CA); On-site; USD 170,000 - 200,000; Full time

Job summary

Ayar Labs in San Jose, CA is seeking a Sr. Engineer, Optical Link Design to advance our co-packaged optics platform.

You will build and apply high‑fidelity models for optical/electrical links, translate device variability into link budgets, and benchmark system‑level performance against measured data. Collaborate with Photonic and AMS teams, expand rigorous link modeling studies, and define component specifications for next‑generation data‑intensive architectures.

Qualifications

• Requires a Bachelor's degree in optics/photonic/physics/electrical engineering or related field.
• Experience in photonics, high-speed link design, and data analysis.
• Strong understanding of high-speed electrical/optical links and photonic components.
• Proficiency in Python for scientific computing and data analysis.

Responsibilities

• Support link modeling studies to define component specs and product spaces.
• Identify device performance metrics and translate variability to link budgets.
• Build system-level models from component data and benchmark against measurements.
• Collaborate with Photonic and AMS teams for cross-domain integration.

Skills

Python

Pandas

NumPy

SciPy

Data analysis

High-speed link design

Photonics

Communication

Verilog-A

Education

Bachelor's degree in Optics/Photonics/Physics/Electrical Engineering

Master's or Ph.D. in Optics/Photonics/Physics/Electrical Engineering

Tools

Verilog-A

Job description

Ayar Labs in San Jose, CA is seeking a Sr. Engineer, Optical Link Design to advance our co-packaged optics platform.

You will build and apply high‑fidelity models for optical/electrical links, translate device variability into link budgets, and benchmark system‑level performance against measured data. Collaborate with Photonic and AMS teams, expand rigorous link modeling studies, and define component specifications for next‑generation data‑intensive architectures.