Electrical Link Architect for High-Speed SerDes & Optics

Ayar Labs; San Jose (CA); On-site; USD 190,000 - 223,000; Full time

Job summary

Ayar Labs is seeking a Senior Staff Engineer in San Jose, CA, to own electrical modeling for silicon photonics I/O platforms. You will design and analyze high-speed links, contributing significant expertise in analog front-end design and DSP. This role requires a Master’s degree and substantial experience in modeling for wireline communication. Join us to explore next-generation architectures and help shape the future of AI compute solutions. Salary range: $190,000 - $223,000.

Qualifications

• 5+ years experience for Sr. Engineer or 8+ years for Staff Engineer.
• Strong working knowledge of analog front-end blocks and DSP.
• Proficient in mixed-signal simulation methodologies.

Responsibilities

• Build and maintain compact models for accurate BER and link-margin prediction.
• Co-design Verilog-A models of electrical/optical interface.
• Run end-to-end link simulations to evaluate device choices.

Skills

High-speed link modeling

Analog front-end design

DSP for wireline communication

Statistical circuit analysis

Python for scientific computing

Education

MS in Electrical Engineering, Physics, or related

Tools

Verilog-A

Cadence Virtuoso / ADE / Spectre

Job description

Ayar Labs is seeking a Senior Staff Engineer in San Jose, CA, to own electrical modeling for silicon photonics I/O platforms. You will design and analyze high-speed links, contributing significant expertise in analog front-end design and DSP. This role requires a Master’s degree and substantial experience in modeling for wireline communication. Join us to explore next-generation architectures and help shape the future of AI compute solutions. Salary range: $190,000 - $223,000.