Sr. Staff Engineer, Electrical Link Architecture

Ayar Labs; San Jose (CA); On-site; USD 190,000 - 223,000; Full time

Job summary

Ayar Labs is seeking a Senior Staff Engineer in San Jose, CA, to own electrical modeling for silicon photonics I/O platforms. You will design and analyze high-speed links, contributing significant expertise in analog front-end design and DSP. This role requires a Master’s degree and substantial experience in modeling for wireline communication. Join us to explore next-generation architectures and help shape the future of AI compute solutions. Salary range: $190,000 - $223,000.

Qualifications

• 5+ years experience for Sr. Engineer or 8+ years for Staff Engineer.
• Strong working knowledge of analog front-end blocks and DSP.
• Proficient in mixed-signal simulation methodologies.

Responsibilities

• Build and maintain compact models for accurate BER and link-margin prediction.
• Co-design Verilog-A models of electrical/optical interface.
• Run end-to-end link simulations to evaluate device choices.

Skills

High-speed link modeling

Analog front-end design

DSP for wireline communication

Statistical circuit analysis

Python for scientific computing

Education

MS in Electrical Engineering, Physics, or related

Tools

Verilog-A

Cadence Virtuoso / ADE / Spectre

Job description

Position: Sr. Staff Engineer, Electrical Link Architecture

Location: San Jose, CA (on-site)

Job Id: 578

# of Openings: 0

Overview

Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co-packaged optics (CPO), we develop silicon photonics solutions that deliver unprecedented bandwidth density and reach at a fraction of the power consumption required to scale next-generation AI models. Backed by industry giants like NVIDIA, AMD, Mediatek, and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Joining our Link Design and Architecture team, you will own the electrical-side modeling that drives our silicon photonics I/O platform – the analog front end, the DSP that closes the link, and the models that make circuits and photonics co-simulate end-to-end. This team is responsible for the robustness and performance of the optical links that power our technology, from component-level modeling through architecture definition, full link analysis, specification development, and yield prediction. Beyond today’s products, the team drives the exploration of next-generation link architectures and directly shapes our long-term technology roadmaps.

Essential Functions

• Build and maintain compact models of the analog front end and the DSP chain at the fidelity needed for accurate BER and link-margin prediction.
• Co-design Verilog-A models of the electrical/optical interface – modulators, photodetectors, and the blocks where circuits and photonics meet – with analog/mixed-signal (AMS) designers.
• Anchor models to silicon by working with validation engineers to reconcile simulation against measurement.
• Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
• Collaborate across AMS, photonics, and validation to keep the modeling stack coherent with the product roadmap.
• Run end-to-end link simulations to evaluate device and architecture choices, informing current product design and future roadmap exploration.

Required Qualifications

• MS in Electrical Engineering, Physics, or a related field.
• 5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
• Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
• Proficiency in Verilog-A and mixed-signal simulation methodologies.
• Experience with statistical circuit analysis methods (corners, Monte Carlo).
• Strong Python skills for scientific computing and data analysis.

Preferred Qualifications

• Prior industry experience architecting and deploying SerDes into a shipping product.
• Ph.D.
• Hands-on experience with silicon bring-up, validation, or link characterization.
• Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
• Familiarity with Cadence Virtuoso / ADE / Spectre.
• Familiarity with optical transceiver principles, modulation formats, and industry standards.

Salary range: $190,000 - $223,000

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.