Senior EDA Tools Lead for ASIC & Physical Verification

Intel; Phoenix (AZ); Hybrid; USD 174,000 - 330,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel’s Design Enablement group seeks a Technical Lead to guide a team delivering ASIC tools/flows, physical verification, and IP sign-off for test chips using Intel PDK collaterals. You will coordinate across Technology Development, EDA vendors, and design teams to deliver high-quality solutions.

You’ll lead teammates, mentor engineers, and ensure delivery within schedule and cost targets while maintaining an inclusive, collaborative culture.

Qualifications

• Minimum qualifications include a degree and 6+ years in related fields.
• Experience mentoring or leading medium-sized teams.
• Experience with physical verification, tape-in and ASIC/PD/PDK domains.

Responsibilities

• Lead and develop a high-performing engineering team and set priorities.
• Drive execution across organizational boundaries and ensure quality delivery.
• Provide technical leadership, mentoring, and coaching to staff.

Skills

Technical management/lead experience

Test chip physical verification

Foundry process knowledge

ASIC/Physical Design/Verification

Technology challenges & process change

Education

BS degree

MS degree

PhD degree

Job description

Intel’s Design Enablement group seeks a Technical Lead to guide a team delivering ASIC tools/flows, physical verification, and IP sign-off for test chips using Intel PDK collaterals. You will coordinate across Technology Development, EDA vendors, and design teams to deliver high-quality solutions.

You’ll lead teammates, mentor engineers, and ensure delivery within schedule and cost targets while maintaining an inclusive, collaborative culture.