Lead EDA Tools Engineer – ASIC & PDK Enablement

Intel; Hillsboro (OR); Hybrid; USD 174,000 - 330,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking a Technical Lead in the Design Enablement group (DTP) at Hillsboro, OR, to lead an engineering team delivering ASIC tools/flows, physical verification, and IP sign-off using Intel PDK collaterals. You will mentor engineers, align schedules with product teams, and drive cross-functional collaboration to meet customer needs.

You will coordinate resources, tackle complex challenges, and promote a culture of accountability and continuous improvement while delivering high-quality

Qualifications

• BS degree with 10+ years or MS with 8+ or PhD with 6+ years in Electrical/Computer Engineering or related field.
• Technical management or lead experience mentoring or leading medium sized teams.
• Experience with ASIC tools/flows, Physical verification/runsets, Tape-in verification and IP sign-off using Intel PDK collaterals.
• Knowledge of advanced-node semiconductor design/verification methodologies and collaboration with EDA vendors and product design teams.

Responsibilities

• Lead and develop a high-performing engineering team by setting priorities, driving execution, and fostering an inclusive, collaborative environment.
• Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution with sound technical judgment.
• Promote team values, accountability, and continuous improvement while guiding employee development and productivity.

Skills

Leadership

Customer focus

Analytical problem solving

Cross-functional collaboration

Communication

Mentoring

Resource management

Education

Electrical/Computer Engineering degree

Tools

ASIC tools/flows

Physical verification

Tape-in verification

EDA tools

Job description

Intel is seeking a Technical Lead in the Design Enablement group (DTP) at Hillsboro, OR, to lead an engineering team delivering ASIC tools/flows, physical verification, and IP sign-off using Intel PDK collaterals. You will mentor engineers, align schedules with product teams, and drive cross-functional collaboration to meet customer needs.

You will coordinate resources, tackle complex challenges, and promote a culture of accountability and continuous improvement while delivering high-quality