Lead EDA Software Engineer (C++, Characterization)

Cadence Design Systems; San Jose (CA); On-site; USD 119,000 - 221,000; Full time

Job summary

Cadence Design Systems in California is seeking an experienced software engineer to contribute to timing analysis tools and frameworks for transistor-level EDA applications.

You will leverage hardcore C++ in Linux, design data structures, and apply ML techniques to improve speed, capacity, and usability across our tooling.

The role emphasizes quality processes and collaboration with cross-functional teams, with competitive compensation and broad benefits.

Qualifications

• 5+ years of experience in development of EDA tools
• Expertise in transistor-level timing, power, noise, aging, reliability, or EMIR analysis
• Strong C++ programming skills in a Linux environment

Responsibilities

• Enhance and expand tooling architecture for timing analysis
• Build new frameworks for analyzing nanoscale effects
• Apply machine learning to improve speed, capacity and usability

Skills

C++

Algorithms

Data structures

Linux/Unix

Software engineering

Education

BS in Computer Science / Electrical Engineering / Computer Engineering

Tools

Unix/Linux

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our expert R&D team as we create technologies and products that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits, powering the communication, IoT, and AI markets.

Key Responsibilities

• Enhance and expand existing tools’ architecture to cover timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.
  

Must-Have Qualifications

• 5+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
• Hardcore C++ knowledge, particularly in a Linux environment.
• Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
• Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.
  

Requirements

• Experience with quality and software processes.
• Proficiency in designing data structures, algorithms, and software engineering principles.
• Ability to analyze transistor or gate-level schematics.
• BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.
  

Nice-to-Have Skills

• Experience in development of circuit simulation or library characterization programs.
• Understanding of SPICE simulation transistor models at a high level.
• Experience with distributed programming, database design, and cloud APIs for distributed computing.
  

Why Cadence?

At Cadence, you’ll work alongside industry leaders and innovators who are passionate about advancing technology. Your contributions will directly impact the development of cutting-edge tools and solutions for the communication, IoT, and AI industries. We foster a collaborative environment where your expertise and ideas will shape the technology of tomorrow.

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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