Senior DRAM Test Engineer (C++, Python, ATE)

Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho seeks a Sr Engineer, TSE-DRAM to develop, debug, and maintain test code for parallel DRAM testing on ATE platforms.

You will design test plans, implement C++ and Python tooling, analyze large probe datasets, and collaborate with global teams to optimize test times and costs. Requirements include a BS in EE/CE/CS or related field and 4 years of experience; knowledge of CMOS, DRAM physics, SPC, and memory testers is preferred.

Qualifications

• Bachelor’s degree in engineering or computer-related field.
• 4 years of experience in DRAM testing or related field.
• Knowledge of digital logic gates, CMOS transistor operation, and DRAM physics.
• Proficiency in C++ for test algorithms.
• Unix/Linux development environments and command line tools.
• Python/Perl scripting for automated testing.

Responsibilities

• Develop, debug, and maintain code for parallel DRAM test flows.
• Design test plans for new tests and test algorithms for DRAM.
• Automate test processes to improve efficiency and reduce test times/costs.
• Collaborate with global teams and provide data-driven insights from probe data.

Skills

CMOS fundamentals

DRAM testing knowledge

C++ programming

Python/Perl scripting

Unix/Linux familiarity

Data analysis SPC

Education

Bachelor's degree in Electrical/ Electronics/ Computer Engineering/ CS/ Mechanical Engineering/ related field

Tools

ATE platforms

Algorithm pattern generation

Test automation tools

Job description

Micron Technology, Inc. in Boise, Idaho seeks a Sr Engineer, TSE-DRAM to develop, debug, and maintain test code for parallel DRAM testing on ATE platforms.

You will design test plans, implement C++ and Python tooling, analyze large probe datasets, and collaborate with global teams to optimize test times and costs. Requirements include a BS in EE/CE/CS or related field and 4 years of experience; knowledge of CMOS, DRAM physics, SPC, and memory testers is preferred.