Senior Digital Mixed-Signal Modeler for Wireless SoCs

Apple; Beaverton (OR); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple is seeking a senior modeling engineer to join the wireless silicon modeling team in Beaverton, Oregon. You will develop behavioral models in SystemVerilog for Analog/RF blocks and SOCs, and prepare testbenches, monitors and tests for pre-silicon verification.

You'll build emulation-ready models, write automation scripts, and collaborate across design and validation teams to ensure delivery on schedule.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Hands-on experience in Mixed-Signal Verification and Real Numbered Modeling of Mixed-Signal Systems.
• Knowledge of wireless technologies: WiFi, BT, UWB or radio systems in general.
• Excellent communication and problem-solving skills.
• Ph.D. or Master’s with 5+ years of experience in modeling of analog/RF circuits.
• Good understanding of emulation technologies and mixed-signal modeling requirements for synthesis-ready models.
• Experience in modeling with SystemC and/or C/C++.
• Experience in writing scripts in languages such as Perl or Python.
• Knowledge of signal processing using Python or Matlab.
• Good understanding of AMS and wireless circuits/systems.
• Experience with SystemC modeling and high-level synthesis.

Responsibilities

• Develop accurate and simulation-efficient analog behavioral models for Analog/RF blocks in SystemVerilog.
• Build and reuse monitors, and checkers for RF, Mixed-Signal and Digital blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking, etc.
• Write scripts for automation of the flow and improve Mixed-Signal verification methodology.
• Develop models that are emulation ready.

Skills

SystemVerilog

Mixed-Signal Verification

Testbench development

Communication

Education

BS in Electrical Engineering

Tools

SystemC

C/C++

Python

Perl

Job description

Apple is seeking a senior modeling engineer to join the wireless silicon modeling team in Beaverton, Oregon. You will develop behavioral models in SystemVerilog for Analog/RF blocks and SOCs, and prepare testbenches, monitors and tests for pre-silicon verification.

You'll build emulation-ready models, write automation scripts, and collaborate across design and validation teams to ensure delivery on schedule.