Senior Digital IP Verification Engineer (UVM SystemVerilog)

NXP Semiconductors; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

NXP Semiconductors is seeking a Digital IP Senior Verification Engineer in Austin, TX. You will define the verification strategy for IP/sub-systems, author verification content, and execute functional verification to ensure specifications are met.

Responsibilities include writing verification plans, stimulus in SystemVerilog/UVM, SVAs, monitors, and testbenches; building and debugging the verification environment; and using AI to boost productivity.

Qualifications

• Minimum BSEE/BSCE/BSCS.
• MSEE/MSCE/MSCS a plus.
• Minimum 5 years of IP or SoC design or verification.
• Proficiency in Verilog/SystemVerilog/UVM required.
• Programming in Python, C/C++, Perl, TCL, etc. a plus.
• Knowledge of ARM AMBA protocols a plus.
• Ability to work independently and in small teams; AI proficiency preferred.

Responsibilities

• Define and write IP verification plans based on requirements documents.
• Write stimulus in SystemVerilog (UVM); develop random test scenarios and directed tests.
• Create and maintain SystemVerilog assertions (SVA) and monitors/drivers for correctness.
• Develop verification environment components and supporting scripts/makefiles.
• Debug failing testcases and trace issues to source; track resolutions.
• Collect code/functional coverage; analyze uncovered events to reach coverage goals.
• Perform assertion-based formal verification; leverage AI to augment work products.

Skills

Verilog

SystemVerilog

UVM

Python

C/C++

Test planning

AI-assisted verification

Education

BSEE/BSCE/BSCS

MSEE/MSCE/MSCS

Tools

Job description

NXP Semiconductors is seeking a Digital IP Senior Verification Engineer in Austin, TX. You will define the verification strategy for IP/sub-systems, author verification content, and execute functional verification to ensure specifications are met.

Responsibilities include writing verification plans, stimulus in SystemVerilog/UVM, SVAs, monitors, and testbenches; building and debugging the verification environment; and using AI to boost productivity.