R-10063878 Digital IP Principal Verification Engineer

NXP Semiconductors; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

NXP Semiconductors in Austin is looking for a Digital IP Principal Verification Engineer responsible for defining and implementing verification strategies for IP or sub-system levels. This role involves executing digital verification, authoring verification documentation, and developing verification test environments.

The ideal candidate has at least 6 years of experience in IP or SoC design, proficiency in System Verilog, and the ability to work independently. NXP values diversity and offers reasonable accommodations for qualified individuals.

Qualifications

• Minimum 6 years of experience in IP or SoC design or verification.
• Proficiency in efficient use of AI to augment generation of work products.
• Knowledge of ARM AMBA® protocols is a plus.

Responsibilities

• Define and write IP verification plans based on requirements documents.
• Write stimulus in System Verilog (UVM) including random test scenarios.
• Develop and maintain portions of a verification environment.

Skills

Digital functional verification

System Verilog

AI productivity tools

RTL coding

Job description

Job Title: Digital IP Principal Verification Engineer

Primary Location: Austin (Oakhill, Office)

Role Summary

Responsible for defining Design Verification strategy, and planning and implementing the verification strategy for an IP or sub-system level.

• Responsible for executing Digital functional verification to guarantee no “functional” fault exist according to Specifications as defined by product architects.
• Author of verification content including Verification-specific documentation, functional simulation models, and verification testbench environment.

Job Responsibilities

• Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications).
• Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
• Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan.
• Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness.
• Developing and maintaining portions of a verification environment including scripts and makefiles.
• Debugging failing testcases to determine source of failure (tool, testcase, checker, verilog RTL) and track resolution.
• Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage.
• Performing assertion-based formal verification of blocks and IPs to ensure they meet requirements.
• Using AI to augment generation of work products and boost productivity.

Job Qualifications

• Minimum 6 years of experience in IP or SoC design or verification.
• Design skills (design documentation, RTL coding, synthesis, static and formal checkers, etc.) a plus.
• Knowledge of ARM AMBA® protocols a plus.
• Ability to work independently and in small teams without close supervision required.
• Proficiency in efficient use of AI to augment generation of work products.

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.