Senior IP Verification Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Benefits offered by this job

Generous benefits package

Equity options

Job summary

NVIDIA Gruppe in Santa Clara is seeking a talented verification engineer to join their multi-media IP team. Responsibilities include verifying multi-media IP designs, collaborating with ASIC design engineers, and developing simulation models. Candidates should have at least 5 years of design verification experience, a solid background in System Verilog, and proficiency in programming with C and Python.

Competitive salaries ranging from $136,000 to $264,500 based on level are offered, along with a generous benefits package. Join NVIDIA as they redefine the future of computing!

Qualifications

• 5+ years of proven design verification experience.
• Expertise in verifying sophisticated IPs using System Verilog.
• Familiarity with AI-enabled IDEs for code development.

Responsibilities

• Drive development of multi-media IP designs.
• Collaborate with design engineers and IP architects.
• Build testbenches and enhance automation flows.

Skills

Design verification experience

Proficiency in System Verilog

Programming in C and Python

Verifying high-level designs

Technical communication skills

Education

BS/MS in Electrical or Computer Engineering

Job description

Overview

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation fueled by great technology and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. This role is part of a front‑end multi‑media IP team responsible for a varied set of multi‑media focused IPs.

Responsibilities

• Participate and help drive the development of NVIDIA multi‑media IP designs with emphasis on first‑pass success.
• Collaborate and partner with ASIC design engineers, IP architects, and other verification engineers to formalize product features.
• Verify IPs using System Verilog and UVM.
• Build testbenches and enhance flows for automation of unit‑level trace‑based testing against reference C models.
• Architect and build verification architecture and associated documents.
• Develop simulation models.
• Manage regression across HLS, Verilog, and FPGA simulations.
• Perform performance testing and analysis.
• Track functional and code coverage and achieve closure.
• Help the team advance verification techniques and methodology.
• Perform IP integration testing into the full chip environment.

Qualifications

• BS/MS in Electrical or Computer Engineering (or equivalent experience).
• 5+ years of proven design verification experience.
• Expertise in verifying sophisticated IPs with System Verilog.
• Experience with verifying High‑Level‑Design (HLS) designs a plus.
• Programming and scripting experience with C and Python.
• Familiarity with using AI‑enabled IDEs for code development.
• Excellent written, verbal, and technical communication skills.
• Demonstrated use of out‑of‑box thinking for creative solutions to highly sticky problems.

Competitive salaries and a generous benefits package are offered. The base salary range is 136,000 USD – 218,500 USD for Level3 and 168,000 USD – 264,500 USD for Level4. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May3, 2026.

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal‑opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.