Senior Verification Engineer

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking an experienced verification engineer to define scope, develop testplans, and build scalable UVM verification infrastructure for complex display/IP silicon.

You will work with C/C++ testbenches and reference models, drive coverage, and collaborate with architects to deliver robust, silicon‑proven designs across global teams.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
• 10+ years of relevant verification experience.
• Deep hands‑on expertise in UVM and SystemVerilog, Verilog, Python, and C/C++.
• Experience with constrained‑random stimulus, functional coverage, and assertion‑based verification.
• Experience with shipped silicon verification and robust software practices.

Responsibilities

• Define verification scope and develop testplans for functional and performance verification.
• Build scalable UVM‑based verification infrastructure.
• Develop UVM testbenches and checkers.
• Work with C/C++‑based testbenches and reference models in HLS.
• Track metrics and drive coverage closure.
• Collaborate with architects on silicon‑proven designs.
• Partner with global NVIDIA sites and external partners to deploy verification flows.

Skills

UVM

SystemVerilog

Verilog

Python

C/C++

Constrained‑random stimulus

Functional coverage

Assertion‑based verification

Ship silicon experience

Education

BS/MS in Electrical Engineering

BS/MS in Computer Engineering

BS/MS in Computer Science

Tools

VCS

Verdi/Debussy

GDB

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years — fueled by great technology and amazing people. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

What You'll Be Doing:

• Define verification scope, develop and drive testplans (functional and performance), and build scalable UVM-based infrastructure.
• Leverage agentic AI to automate repetitive tasks, accelerate debug, and sharpen team efficiency.
• Develop UVM testbenches and checkers.
• Work with C/C++-based testbenches and debug reference models and designs developed in HLS.
• Track metrics and drive coverage closure.
• Critically reason through architectural solutions and partner with our architects to develop well‑crafted, silicon‑proven designs.
• Collaborate across NVIDIA sites globally and work closely with external partners and customers to deploy verification flows, ensure consistent display IP behavior across diverse tool stacks, and debug complex integration issues across organizational boundaries.

What We Need to See:

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience) 10+ years of relevant experience.
• Strong hands‑on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root‑causing complex issues; experience with constrained‑random stimulus, functional coverage, assertion‑based verification, and C/C++-based testbenches — ideally on shipped silicon.
• Proficiency with industry EDA tools (VCS, Verdi/Debussy, GDB) and strong software engineering practices: clean, maintainable code; version control; code review.
• Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low‑power features (clock gating, power domains, retention, entry/exit sequences).
• Self‑starter who dives into unfamiliar sub‑blocks independently, communicates with clarity across time zones and organizational boundaries, and embraces agentic AI to solve daily engineering challenges and multiply team output.

Ways to Stand Out from the Crowd:

• Prior Display Unit Verification experience with familiarity in pixel processing, ISO performance testing, and HLS‑based designs.
• Hands‑on experience verifying display protocols end‑to‑end, MMU/SMMU behavior under ISO traffic, and system‑level low‑power sequences.
• Demonstrated experience shaping architectural specifications and micro‑architecture decisions — not just implementing against them.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward‑thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

NVIDIA uses AI tools in its recruiting processes.

Applications for this job will be accepted at least until August 17, 2026. This posting is for an existing vacancy.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.