Senior Digital Design Engineer - RTL, SoC, Hybrid Role

Powerlattice Technologies Inc; Chandler (AZ); Hybrid; USD 150,000 - 200,000; Full time

Benefits offered by this job

Stock option grant

Health, dental, vision

401(k)

Job summary

Powerlattice Technologies Inc. seeks a Senior Digital Design Engineer to own digital blocks from microarchitecture through RTL in a fast-paced startup setting.

You will work with verification, physical design, and DFT teams to deliver high-quality, timing-robust SoC components. This hybrid role requires 3 onsite days weekly at our Vancouver, WA or Chandler, AZ HQs, with selective remote options for exceptional candidates in Silicon Valley.

Qualifications

• 6+ years of digital IC design experience.
• Strong hands-on RTL development using Verilog/SystemVerilog.
• Experience designing blocks for complex SoCs/ASICs.
• Solid understanding of RTL/microarchitecture and SoC interfaces.
• Experience with EDA tools (Synopsys/Cadence).

Responsibilities

• Develop microarchitecture for digital blocks and subsystems.
• Code and maintain synthesizable RTL.
• Evaluate tradeoffs for performance, power, area, and testability.
• Collaborate with verification, DFT, and physical design teams.
• Assist timing constraints and ECOs.

Skills

Verilog/SystemVerilog RTL

RTL development

Digital IC design

Debugging & problem-solving

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Job description

Powerlattice Technologies Inc. seeks a Senior Digital Design Engineer to own digital blocks from microarchitecture through RTL in a fast-paced startup setting.

You will work with verification, physical design, and DFT teams to deliver high-quality, timing-robust SoC components. This hybrid role requires 3 onsite days weekly at our Vancouver, WA or Chandler, AZ HQs, with selective remote options for exceptional candidates in Silicon Valley.