Technical Lead Digital Design Engineer

Astera Labs; San Jose (CA); On-site; USD 160,000 - 195,000; Full time

Benefits offered by this job

Discretionary bonus

Incentives

Benefits

Job summary

A leading technology company in San Jose is seeking a Staff Design Verification Engineer to oversee the verification lifecycle for complex AI connectivity ASICs. The ideal candidate will have over 5 years of experience, strong proficiency in SystemVerilog/UVM, and skills in debugging and collaborative problem-solving. This position offers a base salary range of $160,000 to $195,000, plus bonuses and a diverse, inclusive working environment.

Qualifications

• 5+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications.
• Strong proficiency with SystemVerilog/UVM-based verification methodologies.
• Experience developing test plans, test sequences, and coverage closure strategies.

Responsibilities

• Execute full verification lifecycle using SystemVerilog/UVM methodologies.
• Develop test sequences and constrained-random stimulus to exercise design functionality.
• Identify and implement coverage measures to ensure comprehensive verification.

Skills

SystemVerilog/UVM

Problem-solving skills

Debugging

Scripting tools (Python/Perl)

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering or related field

Tools

Industry-standard simulators

Revision control systems

Regression systems

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

Astera Labs is seeking a Staff Design Verification Engineer with a talent for breaking code and developing creative verification approaches for complex AI connectivity ASICs. Using your expertise in SystemVerilog, UVM, and problem‑solving skills, you’ll contribute to the functional verification of cutting‑edge designs supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

You’ll be responsible for the full verification lifecycle—from planning to test development to debugging and coverage closure—while collaborating with RTL designers and system validation teams. This is an exciting opportunity to grow your career at a hypergrowth company defining the future of AI infrastructure connectivity.

Key Responsibilities

• Verification Execution
• Execute full verification lifecycle using SystemVerilog/UVM methodologies, from test planning through coverage closure
• Develop test sequences and constrained‑random stimulus to exercise design functionality and corner cases
• Identify and implement coverage measures to ensure comprehensive verification and high‑quality tape‑out
• Debug failures collaboratively with RTL designers, driving issues to root cause resolution
• Deploy hybrid verification techniques combining directed and constrained‑random approaches
• Work with software and system validation teams to develop and execute test plans on emulation platforms
• Infrastructure & Process
• Contribute to verification infrastructure improvements and automation using scripting tools
• Support regression infrastructure and coverage analysis workflows
• Document test plans, coverage strategies, and verification results

Basic Qualifications

• Bachelor's degree in Electrical Engineering; Master's preferred
• 5+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
• Strong proficiency with SystemVerilog/UVM‑based verification methodologies
• Experience developing test plans, test sequences, and coverage closure strategies
• Knowledge of industry‑standard simulators, revision control systems, and regression systems
• Ability to work independently and collaboratively with cross‑functional teams

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with Verification IPs for protocols such as PCIe, CXL, Ethernet, DDR4/5, or similar
• Exposure to formal verification methods
• Working experience with scripting tools (Python/Perl) to automate verification infrastructure
• Experience with directed test methodologies or cache verification

Base salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.