Senior Digital Design Engineer

NVIDIA; Redmond (WA); On-site; USD 136,000 - 218,500; Full time

Benefits offered by this job

Equity options

Inclusive work environment

Comprehensive benefits

Job summary

NVIDIA is seeking a Senior Digital Design Engineer to join its Semi-Custom Silicon products group in Redmond, Washington. In this position, you will engage in the design and implementation of NVLink Fusion based AI infrastructure System-on-Chips, significantly impacting the future of standardized rack-scale AI connectivity.

The ideal candidate will possess a Bachelor's or Master's degree in Electrical or Computer Engineering and have over 5 years of relevant experience, particularly in high-speed connectivity protocols. The role involves collaboration with various engineering teams to achieve design goals while ensuring performance and efficiency.

Qualifications

• 5+ years of relevant work experience.
• Experience with NVLink, PCI-Express, Ethernet, UCIE protocols.
• Proven track record of delivering high bandwidth datapath blocks.

Responsibilities

• Analyze architectural requirements and perform trade-off analysis for implementation.
• Craft micro-architecture specifications and deliver fully verified RTL blocks.
• Collaborate with cross-functional teams to meet project goals.

Skills

High-speed connectivity protocols

ASIC design flows

Analytical skills

Interpersonal skills

Education

Bachelors or Master's Degree in Electrical Engineering or Computer Engineering

Job description

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard‑working engineers crafting and implementing NVLink Fusion based AI infrastructure System‑on‑Chips. You will get a chance to create real impact in a dynamic, industry‑leading, technology‑focused company, while working on NVLink Fusion technology. NVLink Fusion is the enabler for the next generation of standardized rack‑scale AI connectivity.

What You'll Be Doing

• As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade‑off analysis for implementation, and deliver high performance, area and power efficient RTL blocks.
• Craft micro‑architecture specifications, implement in high‑quality RTL, and deliver a fully verified, synthesis and timing clean block.
• Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers to meet the goals of the block in a timely manner.
• Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.

What We Need To See

• Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering.
• 5+ years of relevant work experience.
• Experience working with high‑speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE, etc.
• Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network‑on‑chip, arbiters and schedulers.
• Deep understanding of ASIC design flows and methodology.
• Strong analytical and interpersonal skills, excellent teammate.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 USD – $218,500 USD for Level 3, and $168,000 USD – $264,500 USD for Level 4. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal‑opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.