Senior Digital Design Engineer for AI NVLink Fusion RTL

NVIDIA

Redmond (WA)

Vor Ort

USD 136.000 - 218.500

Vollzeit

14 Tage+

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Benefits dieser Stelle

Equity options
Inclusive work environment
Comprehensive benefits

Zusammenfassung

NVIDIA is seeking a Senior Digital Design Engineer to join its Semi-Custom Silicon products group in Redmond, Washington. In this position, you will engage in the design and implementation of NVLink Fusion based AI infrastructure System-on-Chips, significantly impacting the future of standardized rack-scale AI connectivity.

The ideal candidate will possess a Bachelor's or Master's degree in Electrical or Computer Engineering and have over 5 years of relevant experience, particularly in high-speed connectivity protocols. The role involves collaboration with various engineering teams to achieve design goals while ensuring performance and efficiency.

Qualifikationen

  • 5+ years of relevant work experience.
  • Experience with NVLink, PCI-Express, Ethernet, UCIE protocols.
  • Proven track record of delivering high bandwidth datapath blocks.

Aufgaben

  • Analyze architectural requirements and perform trade-off analysis for implementation.
  • Craft micro-architecture specifications and deliver fully verified RTL blocks.
  • Collaborate with cross-functional teams to meet project goals.

Kenntnisse

High-speed connectivity protocols
ASIC design flows
Analytical skills
Interpersonal skills

Ausbildung

Bachelors or Master's Degree in Electrical Engineering or Computer Engineering

Jobbeschreibung

NVIDIA is seeking a Senior Digital Design Engineer to join its Semi-Custom Silicon products group in Redmond, Washington. In this position, you will engage in the design and implementation of NVLink Fusion based AI infrastructure System-on-Chips, significantly impacting the future of standardized rack-scale AI connectivity.

The ideal candidate will possess a Bachelor's or Master's degree in Electrical or Computer Engineering and have over 5 years of relevant experience, particularly in high-speed connectivity protocols. The role involves collaboration with various engineering teams to achieve design goals while ensuring performance and efficiency.

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