Senior NVLink Fusion Digital Design Engineer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 196,000 - 368,000; Full time

Job summary

NVIDIA seeks a Digital Design Engineer to join the NVLink Fusion team in Santa Clara, CA. You will design high-speed RTL blocks for AI infrastructure, focusing on power, area, and performance.

You’ll craft micro-architecture specs and verify implementations end-to-end. You will collaborate with chip architects, verification engineers, and SoC teams to integrate IP and deliver timing-clean designs, with equity and comprehensive benefits.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering, or equivalent experience.
• 12+ years of relevant work experience in ASIC/SoC design and implementation.

Responsibilities

• Analyze architectural requirements and trade-offs to deliver high-performance RTL blocks.
• Craft micro-architecture specs, implement RTL, and deliver fully verified, timing-clean blocks.
• Collaborate with chip architects, verification engineers, SoC teams to meet block goals and IP integration.

Skills

High-speed protocols knowledge

Collaborative teamwork

Analytical skills

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

NVLink

PCIe

Ethernet

UCIE

Job description

NVIDIA seeks a Digital Design Engineer to join the NVLink Fusion team in Santa Clara, CA. You will design high-speed RTL blocks for AI infrastructure, focusing on power, area, and performance.

You’ll craft micro-architecture specs and verify implementations end-to-end. You will collaborate with chip architects, verification engineers, and SoC teams to integrate IP and deliver timing-clean designs, with equity and comprehensive benefits.