Senior Optical FA Engineer – Fault Isolation & Yield Impact

NVIDIA Corporation; Santa Clara (CA); On-site; USD 144,000 - 265,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Job summary

NVIDIA Corporation is seeking a Senior Failure Analysis Engineer in Santa Clara, CA to drive die-level logic fault localization for advanced semiconductor devices. You will collaborate with Design, Test, and DFT teams to identify root causes, accelerate yield improvements, and ensure high-quality products.

Key responsibilities include failure analysis, use of Advantest 93K for testing, DFT integration, and cross-functional leadership to resolve yield and reliability issues.

Qualifications

• MS degree in Electrical Engineering, Materials Science, Physics, or closely related field.
• 5+ years of direct, hands-on semiconductor failure analysis, yield engineering, or product engineering.
• Strong practical experience with the Advantest 93k test platform.
• Good understanding of DFT basics and logic fault localization.
• Expert level experience on LFI techniques (LVP, EMMI, SDL, OBIRCH, or photon/laser-based).
• Bonus if you also have Teradyne Ultraflex.
• Excellent problem-solving abilities, strong technical communication skills, and a proven track record of driving complex issues to resolution.

Responsibilities

• Die-level Logic Fault Localization: perform complex failure analysis and root cause identification.
• ATE Testing & Debugging: use Advantest 93K to test DUT and enable LVP/SDL/test loops.
• DFT Collaboration: interpret test patterns and guide fault isolation strategies.
• Root Cause Analysis: distinguish design vs fab vs tester-induced failures and recommend actions.
• Cross-Functional Leadership: work with Product, Test, and Foundry Eng to resolve issues.

Skills

Semiconductor failure analysis

DFT basics

LFI techniques

Advantest 93k familiarity

Problem solving

Education

MS in Electrical Engineering

Tools

Advantest 93k platform

Teradyne Ultraflex

Job description

NVIDIA Corporation is seeking a Senior Failure Analysis Engineer in Santa Clara, CA to drive die-level logic fault localization for advanced semiconductor devices. You will collaborate with Design, Test, and DFT teams to identify root causes, accelerate yield improvements, and ensure high-quality products.

Key responsibilities include failure analysis, use of Advantest 93K for testing, DFT integration, and cross-functional leadership to resolve yield and reliability issues.