Senior DFT Engineer: AI-Driven Chip Test & MBIST

Amazon Kuiper Manufacturing Enterprises LLC; El Cajon (CA); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a seasoned DFT engineer to architect and implement DFT solutions for advanced LEO chip SOCs. You will collaborate with ASIC teams across sites to integrate MBIST, clock controls, and JTAG carriers, while aligning with RFIC and Test groups to maximize fault coverage and performance.

Requires strong DFT expertise for deep sub-micron nodes, automation scripting, and experience with AI/ML-assisted workflows.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or experience in electrical engineering field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO chips.
• Contribute to improvement and customization of IPs and DFT methodology with AI flow.
• Work with ASIC design teams to integrate DFT logic like MBIST, clock controls and JTAG controllers.
• Collaborate with RFIC teams to ensure max fault coverage on RF blocks.
• Ensure blocks meet DFT, timing and power targets with implementation team.
• Translate ATE patterns to tester format with Test engineering.
• Jointly bring up the digital portions of the LEO chips with the Test team.

Skills

DFT techniques

MBIST

JTAG

AI/ML flow

RFIC collaboration

Education

Bachelor's degree in Electrical/Communications Engineering

Master's degree in Electrical/Communications Engineering

Tools

DFT automation scripts

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a seasoned DFT engineer to architect and implement DFT solutions for advanced LEO chip SOCs. You will collaborate with ASIC teams across sites to integrate MBIST, clock controls, and JTAG carriers, while aligning with RFIC and Test groups to maximize fault coverage and performance.

Requires strong DFT expertise for deep sub-micron nodes, automation scripting, and experience with AI/ML-assisted workflows.