Senior DFT Engineer for SoC/ASIC Testing & ATPG

Ca One; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Ca One in Santa Clara, CA is seeking a seasoned DFT/ATPG engineer to lead advanced test solutions for SoC and ASIC designs. The role demands hands-on expertise in ATPG pattern generation, MBIST, and RTL-oriented fault analysis, with a focus on controllability, observability, and testability.

You will collaborate with cross-functional teams in a dynamic, high-performance semiconductor program, applying industry-standard DFT tools and clock verification concepts.

Qualifications

• 5+ years hands-on experience in DFT and ATPG for SoC/ASIC designs.
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, including memory test architectures and diagnostics.
• Knowledge of IO Test methodologies for interface and pin level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry standard DFT/ATPG EDA tools.
• Ability to work effectively in fast paced, high performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT/ATPG for SoC/ASIC

DFT fundamentals

ATPG pattern generation

MBIST / memory tests

IO testing

Clock DFT

Digital RTL design

DFT/ATPG tools

Fast-paced environments

Analytical & communication

Education

BE

Job description

Ca One in Santa Clara, CA is seeking a seasoned DFT/ATPG engineer to lead advanced test solutions for SoC and ASIC designs. The role demands hands-on expertise in ATPG pattern generation, MBIST, and RTL-oriented fault analysis, with a focus on controllability, observability, and testability.

You will collaborate with cross-functional teams in a dynamic, high-performance semiconductor program, applying industry-standard DFT tools and clock verification concepts.