Senior DFT Engineer

TYLsemi; United States; Remote; USD 120,000 - 180,000; Full time

Job summary

TYLsemi is seeking a DFT Engineer to own critical DFT implementation and verification for advanced SoC designs. You will push DFT features to maximize test coverage while optimizing test time and power, collaborating closely with RTL, Verification, and PD teams.

The role involves boundary scan, JTAG/IJTAG, ATPG pattern optimization, and MBIST/BISR strategies, with hands-on silicon bring-up and ATE validation. A strong scripting background (Python/Tcl/Perl) is essential.

Qualifications

• Bachelor's or Master's in Electronics/Electrical Engineering.
• 4–7 years of hands-on DFT experience for SoC/ASIC designs.
• Strong proficiency in ATPG, MBIST, LBIST, scan insertion, BSCAN and IJTAG; experience with industry DFT tools.

Responsibilities

• Develop and implement DFT architecture including scan insertion, compression, and hierarchical DFT.
• Generate and optimize ATPG patterns for various fault models and perform failure diagnosis.
• Design, integrate, and verify MBIST controllers, repair mechanisms (BISR), and memory test strategies.
• Implement and verify Boundary Scan (BSCAN), JTAG, and IJTAG (IEEE 1687) infrastructure.
• Perform DFT static timing analysis (STA), constraint development, and timing closure with PD teams.
• Execute DFT verification including pre-silicon simulations and Gate-Level Simulation (GLS).
• Support silicon bring-up, ATE pattern validation, and post-silicon debugging.
• Collaborate with RTL, Verification, Physical Design, and Test Engineering to resolve DFT issues.
• Analyze coverage metrics and improve test quality.

Skills

ATPG

LBIST

MBIST

Scan insertion

JTAG/IJTAG

Python scripting

Silicon bring-up

Education

Bachelor's/Master's in Electronics/Electrical Engineering

Tools

DFT insertion tools

Pattern generation tools

Simulation tools

GLS tools

Job description

Role Overview

We are looking for a DFT Engineer with solid hands‑on experience to own key aspects of DFT implementation and verification for advanced SoC designs. You will drive DFT features to achieve high test coverage while optimizing for test time and power.

What You’ll Do

• Develop and implement DFT architecture including scan insertion, compression, and hierarchical DFT.


• Generate and optimize ATPG patterns for various fault models (stuck‑at, transition, path delay, etc.) and perform failure diagnosis.


• Design, integrate, and verify MBIST controllers, repair mechanisms (BISR), and memory test strategies.


• Implement and verify Boundary Scan (BSCAN), JTAG, and IJTAG (IEEE 1687) infrastructure.


• Perform DFT static timing analysis (STA), constraint development, and timing closure in collaboration with PD teams.


• Execute DFT verification including pre‑silicon simulations and Gate‑Level Simulation (GLS).


• Support silicon bring‑up, ATE (Automated Test Equipment) pattern validation, and post‑silicon debug.


• Work closely with cross‑functional teams (RTL, Verification, Physical Design, Test Engineering) to resolve DFT issues.


• Analyze coverage metrics and improve test quality.

What We’re Looking For

• Bachelor’s/Master’s degree in Electronics/Electrical Engineering.


• 4-7 years of experience in DFT for SoC/ASIC designs.


• Strong proficiency in ATPG, MBIST, LBIST, scan compression, BSCAN and IJTAG.


• Experience with industry tools for DFT insertion, pattern generation, and simulation.


• Hands‑on silicon bring‑up and debug experience.


• Proficiency in scripting (Python,Tcl, Perl) for automation.