Senior Designer - High-Speed Optical Modulators (Remote)

Ciena Corporation; Northern (KY); Hybrid; USD 133,000 - 213,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision plans

401(k) with matching

Employee stock purchase program

Paid time off

Job summary

Ciena Corporation is seeking a Senior Designer to lead high-speed optical modulator development for next-generation coherent systems. You will own RF/optical co-design, modeling, layout, characterization, and design closure, guiding modulator PIC functions and related blocks.

You will collaborate across teams to ensure system-level constraints, reliability, packaging, and multi-chip integration are addressed, while providing hands-on technical leadership.

Qualifications

• PhD or equivalent in EE/PH/photonic field with strong experimental and modeling background.
• Five+ years in high-speed electro-optic modulators or PIC technologies.
• Experience with heterogeneous integration and PIC design challenges.

Responsibilities

• Serve as technical authority for heterogeneously integrated optical modulator PICs.
• Design or guide related PIC functions such as passive routing, couplers, and polarization elements.
• Refine models using measurement data and close loop between simulation, layout, fabrication, and performance.
• Provide senior technical direction and reviews on modulator design choices.

Skills

EO modulator physics

RF/optical co-design

Traveling-wave electrodes

Velocity/impedance matching

Bandwidth optimization

High-speed measurement

Project leadership

Education

PhD in electrical engineering or related field

Tools

HFSS

ADS

FDTD

EME

Eigenmode Solvers

Job description

Ciena Corporation is seeking a Senior Designer to lead high-speed optical modulator development for next-generation coherent systems. You will own RF/optical co-design, modeling, layout, characterization, and design closure, guiding modulator PIC functions and related blocks.

You will collaborate across teams to ensure system-level constraints, reliability, packaging, and multi-chip integration are addressed, while providing hands-on technical leadership.