Senior Design Verification Engineer (remote)

Chelsea Search Group, Inc.; Boston (MA); Remote; USD 110,000 - 160,000; Full time

Job summary

A leading company is seeking a Senior Design Verification Engineer to develop and execute complex verification plans for digital designs. This remote position requires expertise in SoC verification, SystemVerilog, and UVM among other qualifications, offering a competitive salary and comprehensive benefits.

Benefits

Bonus

Benefits

401k

Stock Options

Qualifications

• 5-15 years of hands-on experience in SoC verification using UVM.
• Experience with digital design concepts and ASIC development flow.
• Ability to work collaboratively across teams.

Responsibilities

• Develop and execute verification plans for digital designs.
• Create and maintain testbenches, test cases, and test vectors.
• Document verification strategies and results.

Skills

SoC verification

SystemVerilog

UVM

C++

Python

Gate Level Simulation

Digital design concepts

ASIC development flow

Education

BSEE/MSEE

Tools

Synopsys verification tools

Git

Job description

Senior Design Verification Engineer
Remote / work from any US location
US Citizen or US Permanent Resident preferred
Full-time/employee + Bonus, Benefits, 401k, Stock Options

Responsibilities:
• Develop and execute verification plans for digital designs using SystemVerilog and UVM
• Create and maintain testbenches, test cases, and test vectors
• Contribute to the development of novel methodologies and verification techniques
• Run simulations to verify design against specifications and analyze results, identify issues, and debug designs
• Implement coverage tracking and metrics
• Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
• Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.

Required Skills & Experience:
• BSEE/MSEE with 5-15 years of hands-on experience in SoC verification using UVM
• Experience in Gate Level Simulation (GLS) setup and process corner failure analysis
• Experience with digital design concepts and ASIC development flow
• Experience writing and debugging RTL using SystemVerilog
• Programming experience using C, C++, and/or Python/Perl
• Ability to work collaboratively across teams and communicate effectively
• Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
• Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects

Preferred Skills:
• Experience verifying RISC-V based systems
• Experience with emulation or FPGA prototyping
• Experience with formal verification methodologies
• Experience with the Chisel hardware description language
• Experience verifying high-speed interfaces such as PCIe and DDR
• Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

DESIGN VERIFICATION GROUP on LinkedIn: https://www.linkedin.com/groups/3989573/