Senior Design Verification Engineer (remote)

Chelsea Search Group, Inc.; Los Angeles (CA); Remote; USD 100,000 - 150,000; Full time

Job summary

An established industry player is seeking a Senior Design Verification Engineer to join their innovative team. This remote role involves developing and executing verification plans for cutting-edge digital designs using SystemVerilog and UVM. You'll create comprehensive testbenches, run simulations, and document verification strategies, ensuring the highest quality in design verification. The ideal candidate will have extensive experience in SoC verification and a collaborative spirit, ready to tackle complex challenges in a fast-paced environment. If you're passionate about digital design and eager to contribute to groundbreaking projects, this opportunity is for you.

Benefits

Benefits

401k

Stock Options

Qualifications

• 5+ years of SoC verification experience using UVM.
• Proficient in SystemVerilog and debugging RTL.
• Strong background in digital design and ASIC development.

Responsibilities

• Develop and execute verification plans using SystemVerilog and UVM.
• Create and maintain testbenches and test cases.
• Document verification strategies and results comprehensively.

Skills

SoC verification

SystemVerilog

UVM

C/C++/Python/Perl programming

Digital design concepts

Debugging RTL

Team collaboration

Multi-tasking

Education

BSEE/MSEE

Tools

Synopsys verification tools (VCS, Verdi, Spyglass)

Git

Job description

Senior Design Verification Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Responsibilities:

1. Develop and execute verification plans for digital designs using SystemVerilog and UVM
2. Create and maintain testbenches, test cases, and test vectors
3. Contribute to the development of novel methodologies and verification techniques
4. Run simulations to verify design against specifications and analyze results, identify issues, and debug designs
5. Implement coverage tracking and metrics
6. Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies
7. Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.

Required Skills:

1. BSEE/MSEE with 5+ years of hands-on experience in SoC verification using UVM
2. Experience in gate level simulation setup and process corner failure analysis
3. Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
4. Experience with digital design concepts and ASIC development flow
5. Experience writing and debugging RTL using SystemVerilog
6. Programming experience using C, C++, and/or Python/Perl
7. Ability to work collaboratively across teams and communicate effectively
8. Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects

Preferred Skills:

1. Experience verifying high-speed interfaces such as PCIe and DDR
2. Experience verifying RISC-V based systems
3. Experience with emulation or FPGA prototyping
4. Experience with formal verification methodologies
5. Experience with the Chisel hardware description language
6. Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

#SoC #UVM #SystemVerilog #SoCDesign #DesignVerification