Verification Engineer

Akkodis; Redmond (WA); Remote; USD 125,000 - 150,000; Full time

Job summary

Akkodis is looking for a Silicon Verification Engineer for a 4-month contract in Redmond, WA. This remote role focuses on generating and implementing verification plans, requiring proficiency in SystemVerilog and UVM along with hands-on experience in mixed signal verification. Ideal candidates will possess strong collaboration and communication skills with a background in engineering disciplines.

Benefits

Medical insurance

Dental coverage

Vision insurance

Life insurance

Short-term disability

401K plan

Qualifications

• Minimum 2+ years of experience with SystemVerilog and UVM.
• Experience in Mixed Signal Verification and Design Verification Methodology.
• Effective communication and teamwork skills.

Responsibilities

• Define, document, and implement a UVM verification environment including agents and scoreboards.
• Write and implement test plans by developing tests, test generators, and coverage.
• Run tests on RTL and Gate Level Netlists, debug failures and recommend fixes.

Skills

SystemVerilog

UVM

Mixed Signal Verification

Design Verification Methodology

Effective communication

Collaboration

Education

Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

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Direct message the job poster from Akkodis

Akkodis is seeking a Silicon Verification Engineer – 100% Remote (PST),for a 4-month Contract with a client in Redmond, WA.

Rate Range: $35.00 - $41.00 P/HR.; The rate may be negotiable based on experience, education, geographic location, and other factors.

Candidate Requirements

• Years of Experience Required: 2+, Ideally 3-6 overall years of experience in the field.

• Degrees or certifications required: Not required but nice to have.

• Disqualifiers: Candidates must have a strong grasp of SystemVerilog and UVM. If they only have IT experience and are not familiar with VMM/ OVM/ UVM they will not be eligible for the role.

Top 3 Hard Skills Required + Years of Experience

1. Minimum 2+years experience with SystemVerilog and UVM.

2. Minimum 2+years experience with Mixed Signal Verification.

3. Minimum 2+years experience with Design Verification Methodology.

Summary:

The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:

• Define, document, and implement a UVM verification environment including agents and scoreboards

• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral

• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

• Support post-silicon verification activities of the products working with design and product teams

Skills:

• Proficient in using Verilog and VMM/OVM/UVM

• Experience in pre and post-silicon verification test flow and automated test benches

• Effective communication, collaboration, and teamwork skills

Education/Experience:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree nice to have

2-4 years of relevant experience required.

If you are interested in this role, then please click APPLY NOW. For other opportunities available at Akkodis, or any questions, feel free to contact me at [e-mail].

Equal Opportunity Employer/Veterans/Disabled

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, an EAP program, commuter benefits, and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable. Disclaimer: These benefit offerings do not apply to client-recruited jobs and jobs that are direct hires to a client.

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit https://www.akkodis.com/en/privacy-policy.

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

· The California Fair Chance Act

· Los Angeles City Fair Chance Ordinance

· Los Angeles County Fair Chance Ordinance for Employers

· San Francisco Fair Chance Ordinance

Seniority level

• Seniority level

  Associate

Employment type

• Employment type

  Contract

Job function

• Job function

  Engineering and Information Technology

• Industries

  IT Services and IT Consulting and Electric Power Generation

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