Senior Design Verification Engineer

Intuitive; Sunnyvale (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading company in the tech industry is seeking a dedicated verification engineer to ensure the functional correctness of FPGA systems. The role involves hands-on testbench development, collaboration with design teams, and comprehensive verification coverage through advanced testing methodologies. If you are passionate about hardware verification and enjoy working in a dynamic environment, this is the opportunity for you.

Qualifications

• Experience in verification of FPGA’s and RTL functional correctness.
• Hands-on experience with testbench development.

Responsibilities

• Start-to-finish verification from test planning to closure.
• Develop constrained random tests for comprehensive coverage.

Skills

Verification

Collaboration

Debugging

Tools

UVM

Job description

Job Description

Primary Function of Position:

• Verification of FPGA’s on daVinci systems for RTL functional correctness.

Roles & Responsibilities:

• Responsibilities include start-to-finish verification, from test planning to closure, using coverage metrics.
• Hands-on testbench development using UVM.
• Collaborate with the design team to review specifications and architecture, extract features, and define verification plans and coverage models.
• Develop constrained random tests to ensure comprehensive verification coverage.
• Implement functional cover groups and SVA to verify randomness and coverage.
• Debug failures, track bugs, analyze coverage metrics, and ensure coverage closure.