Senior Design Verification Engineer

Correct Designs; Austin (TX); Hybrid; USD 120,000 - 160,000; Full time

Job summary

A leading company in Austin, Texas is seeking a Senior Design Verification Engineer to work on cutting-edge projects in AI, Machine Learning, and more. This role offers long-term stability, generous hourly rates, and opportunities for both in-person and remote work. Ideal candidates will have extensive experience in verification and a strong background in SystemVerilog and UVM.

Benefits

Healthcare benefits

Retirement benefits

Qualifications

• 8+ years of proven verification experience in hardware development.
• Strong background in SystemVerilog and UVM methodologies.

Responsibilities

• Verify complex design blocks using complex SV/UVM verification environments.
• Develop and execute pre-silicon verification test plans.

Skills

Debugging

Analytical Skills

Problem Solving

Communication

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Bachelor's in Computer Engineering

Master's in Computer Engineering

Bachelor's in Computer Science

Master's in Computer Science

Tools

DVE

Verdi

Perl

Ruby

Make

Job description

Join to apply for the Senior Design Verification Engineer role at Correct Designs.

Looking for new challenges? Would you like the variety of a contract position along with long-term stability and benefits? Correct Designs can offer it all.

Correct Designs is currently seeking talented Verification Engineers with prior SystemVerilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities include projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates will support verification of advanced CPU/GPU based SOCs.

Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers enjoy respected long-term roles with generous hourly rates in excellent team environments. Contracts typically last 3 years, with shorter and longer options available. We are well respected in the Design Verification community, with clients always seeking new CDI engineers. If you need a break between contracts, you can take it, knowing plenty of work will be available upon your return. For those seeking stability, moving to the next contract is seamless. Correct Designs also provides healthcare and retirement benefits.

We are based in Austin, Texas, with clients throughout the US. Opportunities for both in-person and remote work are available.

Whether you are an experienced veteran seeking new challenges or a talented engineer looking to broaden your experience, we offer exciting career options.

Responsibilities

• Verify complex design blocks using complex SV/UVM verification environments
• Develop and execute pre-silicon verification test plans
• Develop directed and random verification tests to validate block and IP functionality
• Develop verification components and tools
• Develop verification functional coverage using industry standard tools/methods
• Debug regression failures
• Replicate functional issues found externally or post-silicon; review/enhance tests to verify bug fixes

Required Skills And Experience

• 8+ years of proven verification experience in hardware development
• Strong background in SystemVerilog and UVM methodologies
• Strong debugging skills and experience with tools like DVE/Verdi
• Proficiency in Object-Oriented programming, computer architecture, and data structures
• Strong analytical and problem-solving skills with attention to detail
• Excellent interpersonal and communication skills
• Comfortable working across geographies

Desired Skills

• Experience architecting/developing verification environments and scripting (Perl, Ruby, Make, etc.)
• Experience in formal verification, RTL design, or software development

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science