Senior Design Technologist for SoC & PPA Excellence

MIPS Holding Inc; Richardson (TX); On-site; USD 171,000 - 296,000; Full time

Job summary

GlobalFoundries is seeking a Sr. Principal Engineer – Design Technology to lead design technology initiatives for advanced SoC projects in the U.S.

You will translate process tech capabilities into design guidelines, drive PPA optimization, and influence sign-off flows for next‑gen nodes. The role demands deep fabrication knowledge, hands‑on experience with EDA tools (Cadence, Synopsys, Siemens), strong leadership, and the ability to collaborate across architecture, RTL, and physical design

Qualifications

• 15+ years of experience in SoC design, physical design, EDA flows/methodologies and/or semiconductor process integration.
• Deep understanding of semiconductor fabrication processes on advanced process nodes and technology PDKs.
• Hands-on experience with timing, power and signal integrity in modern SoCs.
• Proven track record of developing SoC implementation flows on advanced nodes.
• Strong knowledge of industry-standard EDA tools for design and simulation.

Responsibilities

• Translate process technology capabilities into design guidelines and methodology improvements for best-in-class PPA, DFM and yield optimization.
• Define technology aware design methodologies and sign-off flows for advanced nodes with PPA and DFM goals.
• Drive technology benchmarking, roadmap, and integration of new methodologies with EDA tool vendors.
• Mentor junior engineers and provide technical guidance across teams.

Skills

SoC design expertise

PPA optimization

Problem solving

Cross-functional collaboration

Education

Bachelor’s or Master’s in electrical/computer engineering or related field

Tools

Cadence

Synopsys

Siemens EDA

Job description

GlobalFoundries is seeking a Sr. Principal Engineer – Design Technology to lead design technology initiatives for advanced SoC projects in the U.S.

You will translate process tech capabilities into design guidelines, drive PPA optimization, and influence sign-off flows for next‑gen nodes. The role demands deep fabrication knowledge, hands‑on experience with EDA tools (Cadence, Synopsys, Siemens), strong leadership, and the ability to collaborate across architecture, RTL, and physical design