Senior ASIC Digital Design Lead: Processor Core & SoC RTL

MIPS Holding Inc

Santa Clara (CA)

On-site

USD 167,000 - 275,000

Full time

14 days+
Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Job summary

GlobalFoundries is seeking a PMTS Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and subsystems. The role requires deep processor design expertise and the ability to drive complex SoC programs from concept through silicon bring-up.

You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to optimize performance, power, and area while meeting schedules.

Qualifications

  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
  • 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
  • Expert-level RTL design experience using Verilog/SystemVerilog.
  • Strong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.
  • Experience with industry-standard EDA tools and design flows.
  • Strong debugging and problem-solving skills.

Responsibilities

  • Develop and implement microarchitecture for CPU cores, cache subsystems, MMU, interconnects, and system controllers.
  • Translate architectural specifications into RTL designs using Verilog/SystemVerilog; drive performance, power, and area efficiency.
  • Lead critical processor design initiatives across multiple blocks and mentor engineers.
  • Collaborate with verification, physical design, DFT, firmware, and software teams to meet targets.
  • Support silicon bring-up, debug, characterization, and production ramp activities.

Skills

Processor design
Technical leadership
Cross-functional collaboration
Debugging and problem solving

Education

Bachelor's or Master's in electrical/computer engineering

Tools

Verilog/SystemVerilog
EDA tools

Job description

GlobalFoundries is seeking a PMTS Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and subsystems. The role requires deep processor design expertise and the ability to drive complex SoC programs from concept through silicon bring-up.

You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to optimize performance, power, and area while meeting schedules.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior ASIC Digital Design Engineer: Processor RTL & IP
Senior ASIC Digital Design Engineer: Processor RTL & IP

GlobalFoundries • Santa Clara (CA)

On-site
USD 167,000 - 275,000
Senior PMTS ASIC Digital Design Architect
Senior PMTS ASIC Digital Design Architect

GlobalFoundries inc. • Santa Clara (CA), Northern (KY)

Hybrid
USD 167,000 - 275,000
PMTS ASIC Digital Design IP ENGINEERING
PMTS ASIC Digital Design IP ENGINEERING

GlobalFoundries • Santa Clara (CA)

On-site
USD 167,000 - 275,000
Senior Manager, ASIC Processor IP Design
Senior Manager, ASIC Processor IP Design

GlobalFoundries inc. • Santa Clara (CA), Northern (KY)

Hybrid
USD 165,000 - 275,000
PMTS ASIC Digital Design IP ENGINEERING
PMTS ASIC Digital Design IP ENGINEERING

MIPS Holding Inc • Santa Clara (CA)

On-site
USD 167,000 - 275,000
PMTS ASIC Digital Design IP ENGINEERING
PMTS ASIC Digital Design IP ENGINEERING

GlobalFoundries inc. • Santa Clara (CA), Northern (KY)

On-site
USD 167,000 - 275,000
Lead Architect, Custom Silicon & SoCs
Lead Architect, Custom Silicon & SoCs

GLOBALFOUNDRIES U.S. INC. • Richardson (TX)

On-site
USD 132,000 - 242,000
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING

GlobalFoundries inc. • Santa Clara (CA), Northern (KY)

On-site
USD 165,000 - 275,000
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING

MIPS Holding Inc • Santa Clara (CA)

On-site
USD 187,000 - 255,000
Senior Design Technologist for SoC & PPA Excellence
Senior Design Technologist for SoC & PPA Excellence

MIPS Holding Inc • Richardson (TX)

On-site
USD 171,000 - 296,000