Senior Design Engineer: CIM & Memory Architect

Micron Technology; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical, dental, vision

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a Senior Design Engineer (or Staff Design Engineer) in the NVE Design Engineering Core group to contribute to memory product development with core and mixed-signal circuit expertise.

You will design, analyze, and optimize array circuits for NAND Flash and Compute‑in‑Memory (CIM) concepts, while collaborating with Firmware, Analog, and Validation teams. The role involves planing wordline/bitline architectures, performing die size analyses, and running SPICE-based

Qualifications

• Minimum: MS in electrical engineering; PhD preferred.
• 4+ years NAND design experience; CIM projects led or contributed.
• Strong fundamentals in semiconductor and analog/mixed-signal circuit design.
• Proficiency in Python and scripting; automation and data handling beneficial.

Responsibilities

• Develop array waveforms with timing and biasing for NAND Flash and CIM/near-memory compute modes.
• Collaborate with Firmware, Analog, and Design validation teams.
• Plan wordline/bitline path architecture to meet area, performance and power specs.
• Analyze die size costs and benefits; review NAND power consumption with cross-functional teams.
• Generate schematic blocks and run sub-system/full-chip simulations; oversee layout integration.
• Build Python-based AI utilities interfacing with EDA tools for automation and predictive design.
• Review and create technical documentation; support CIM use cases in memory arrays.
• Coordinate with Product Eng, Test, Process Integration, Assembly, and Marketing.

Skills

Self-motivation

Semiconductor physics

Analog/mixed-signal design

Python coding

Version control

Problem solving

Education

MS in electrical engineering

PhD preferred

Tools

Cadence design

LVS/DRC tools

HSPICE

Verilog

Fast SPICE

Job description

Micron Technology, Inc. seeks a Senior Design Engineer (or Staff Design Engineer) in the NVE Design Engineering Core group to contribute to memory product development with core and mixed-signal circuit expertise.

You will design, analyze, and optimize array circuits for NAND Flash and Compute‑in‑Memory (CIM) concepts, while collaborating with Firmware, Analog, and Validation teams. The role involves planing wordline/bitline architectures, performing die size analyses, and running SPICE-based